The document describes the design and implementation of an efficient interpolator for wireless communication systems using FPGA. It proposes a multiplier-less technique using distributed arithmetic look-up tables (DALUT) that replaces multiply-accumulate operations with LUT accesses. A 66th-order half-band polyphase FIR structure is implemented using the DALUT approach on Spartan-3E and Virtex2Pro FPGAs. Results show the proposed design achieves maximum frequencies of 92.859MHz on Virtex Pro and 61.6MHz on Spartan 3E while consuming fewer resources than a traditional MAC-based design.
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
Design and implementation of DA FIR filter for bio-inspired computing archite...IJECEIAES
This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DAfinite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.
This document summarizes a research paper on designing low power digit serial finite impulse response (FIR) filters using multiple constant multiplication (MCM) techniques. It proposes an architecture that optimizes the area of digit serial MCM operations at the gate level by considering the implementation costs of digit serial addition, subtraction and shift operations. An algorithm is presented to design digit serial FIR filters under a shift-adds architecture to reduce area compared to designs using generic digit serial multipliers. Experimental results show the technique leads to lower complexity digit serial MCM designs.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
AN EFFICIENT DSP ARCHITECTURE DESIGN IN FPGA USING LOOP BACK ALGORITHMIJARIDEA Journal
Abstract— Advanced flag processors assume a noteworthy part in electronic gadgets, bio restorative applications, correspondence conventions. Effective IC configuration is a key variable to accomplish low power and high throughput IP center improvement for convenient gadgets. Computerized flag processors assume a huge parts progressively figuring and preparing yet region overhead and power utilization are real disadvantages to accomplish productive outline requirements. Adaptable DSP engineering utilizing circle back calculation is a proposed way to deal with beat existing outline limitations. For instance, plan of 8 point FFT engineering requires 3 phases for butterfly calculation unit that 48 adders and 12 multipliers prompts high power and territory utilization. To lessen range and power, Loop back calculation is proposed and it requires 16 adders and 4 multipliers for general outline. Likewise outline of various DSP layouts like FFT, First request FIR channel and Second request FIR channel is acquainted and mapping in with the design as preparing component and applying the circle back calculation. In the outline of FFT,FIR formats adders, for example, parallel prefix viper, move and include multiplier, baugh-wooley multiplier are utilized to break down effective plan of DSP engineering. Recreation and examination of inactivity, territory, control productivity with the current structures are happens utilizing model sim 6.4a and combine utilizing Xilinx 14.3 ISE.
Keywords— Baugh-UWooley Multiplier, Loop Back Algorithm, Parallel Prefix Adders.
Memory Based Hardware Efficient Implementation of FIR FiltersDr.SHANTHI K.G
The document summarizes memory-based hardware efficient implementations of finite impulse response (FIR) filters. FIR filters are commonly used in digital signal processing systems. The paper explores memory-based realization of FIR filters using techniques like direct memory implementation and distributed arithmetic. Direct memory implementation replaces multiplications with filter coefficients with pre-computed values stored in a read-only memory (ROM) or lookup table (LUT). Distributed arithmetic implements MAC operations using LUT accesses and shift-accumulation, making it well-suited for field-programmable gate arrays. The paper compares different memory-based architectures for FIR filters in terms of ROM size, delay, and throughput to assist in selecting the best architecture for a given application.
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...IOSRJECE
Now a day’s numerous wireless communication standards have raised additional stringent requirements on each throughput and flexibility for FFT computation. Advanced wireless systems support multiple standards to satisfy the demands of user application necessities. A wireless system whereas supporting multiple standards should also satisfy performance necessities of these supported standards. Meeting performance requirements of multiple standards is a challenge while designing a system. Fast Fourier transformations, a kernel processing task in communication systems, are studied intensively for efficient software and hardware implementations. To design an efficient system, it's necessary to efficiently design its performance critical component. each system must meet stringent design parameters like high speed, low power, low area, low cost, high flexibility and high scalability, designing FFT processor to support multiple wireless standards whereas meeting the above such performance necessities is a difficult task. This paper proposed a highly efficient scalable architecture, software tools design, and design implementation. The reconstruction of the FFT computation flow is design into a scalable structure. The FFT can be easily expanded for any-point FFT computation. The various parameters satisfied the conditions, gives proper and efficient outputs as compare to other platforms.
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithm...IOSR Journals
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance. Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
Design and implementation of DA FIR filter for bio-inspired computing archite...IJECEIAES
This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DAfinite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.
This document summarizes a research paper on designing low power digit serial finite impulse response (FIR) filters using multiple constant multiplication (MCM) techniques. It proposes an architecture that optimizes the area of digit serial MCM operations at the gate level by considering the implementation costs of digit serial addition, subtraction and shift operations. An algorithm is presented to design digit serial FIR filters under a shift-adds architecture to reduce area compared to designs using generic digit serial multipliers. Experimental results show the technique leads to lower complexity digit serial MCM designs.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
AN EFFICIENT DSP ARCHITECTURE DESIGN IN FPGA USING LOOP BACK ALGORITHMIJARIDEA Journal
Abstract— Advanced flag processors assume a noteworthy part in electronic gadgets, bio restorative applications, correspondence conventions. Effective IC configuration is a key variable to accomplish low power and high throughput IP center improvement for convenient gadgets. Computerized flag processors assume a huge parts progressively figuring and preparing yet region overhead and power utilization are real disadvantages to accomplish productive outline requirements. Adaptable DSP engineering utilizing circle back calculation is a proposed way to deal with beat existing outline limitations. For instance, plan of 8 point FFT engineering requires 3 phases for butterfly calculation unit that 48 adders and 12 multipliers prompts high power and territory utilization. To lessen range and power, Loop back calculation is proposed and it requires 16 adders and 4 multipliers for general outline. Likewise outline of various DSP layouts like FFT, First request FIR channel and Second request FIR channel is acquainted and mapping in with the design as preparing component and applying the circle back calculation. In the outline of FFT,FIR formats adders, for example, parallel prefix viper, move and include multiplier, baugh-wooley multiplier are utilized to break down effective plan of DSP engineering. Recreation and examination of inactivity, territory, control productivity with the current structures are happens utilizing model sim 6.4a and combine utilizing Xilinx 14.3 ISE.
Keywords— Baugh-UWooley Multiplier, Loop Back Algorithm, Parallel Prefix Adders.
Memory Based Hardware Efficient Implementation of FIR FiltersDr.SHANTHI K.G
The document summarizes memory-based hardware efficient implementations of finite impulse response (FIR) filters. FIR filters are commonly used in digital signal processing systems. The paper explores memory-based realization of FIR filters using techniques like direct memory implementation and distributed arithmetic. Direct memory implementation replaces multiplications with filter coefficients with pre-computed values stored in a read-only memory (ROM) or lookup table (LUT). Distributed arithmetic implements MAC operations using LUT accesses and shift-accumulation, making it well-suited for field-programmable gate arrays. The paper compares different memory-based architectures for FIR filters in terms of ROM size, delay, and throughput to assist in selecting the best architecture for a given application.
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...IOSRJECE
Now a day’s numerous wireless communication standards have raised additional stringent requirements on each throughput and flexibility for FFT computation. Advanced wireless systems support multiple standards to satisfy the demands of user application necessities. A wireless system whereas supporting multiple standards should also satisfy performance necessities of these supported standards. Meeting performance requirements of multiple standards is a challenge while designing a system. Fast Fourier transformations, a kernel processing task in communication systems, are studied intensively for efficient software and hardware implementations. To design an efficient system, it's necessary to efficiently design its performance critical component. each system must meet stringent design parameters like high speed, low power, low area, low cost, high flexibility and high scalability, designing FFT processor to support multiple wireless standards whereas meeting the above such performance necessities is a difficult task. This paper proposed a highly efficient scalable architecture, software tools design, and design implementation. The reconstruction of the FFT computation flow is design into a scalable structure. The FFT can be easily expanded for any-point FFT computation. The various parameters satisfied the conditions, gives proper and efficient outputs as compare to other platforms.
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithm...IOSR Journals
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance. Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline
An fpga implementation of the lms adaptive filter eSAT Journals
This document describes an FPGA implementation of the Least Mean Square (LMS) adaptive filter algorithm for active vibration control. It compares fixed-point and floating-point implementations in terms of area usage and performance. The LMS algorithm is implemented using a finite state machine model with separate modules for operations like filtering, error estimation, and weight adaptation. Both implementations utilize this structural model. The fixed-point version uses 16-bit integers and fractions, while the floating-point version leverages IP cores. Results show the floating-point implementation has better accuracy and resource utilization than the fixed-point version for active vibration control applications on FPGAs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
This document summarizes a research paper that proposes an efficient VLSI implementation of a pipelined fast Fourier transform (FFT). The key aspects are:
1) A single-path delay feedback (SDF) pipeline architecture is adopted to implement the FFT processor. This architecture requires less memory space and has lower power consumption than existing designs.
2) A reconfigurable complex multiplier and bit-parallel multipliers are used instead of read-only memories to store twiddle factors. This eliminates the need for ROMs and reduces power consumption.
3) The proposed FFT architecture contains three types of processing elements - a complex constant multiplier, delay buffers, and extra units for IFFT computation. It achieves a
FIR Filter Implementation by Systolization using DA-based DecompositionIDES Editor
In this paper we present 1D and 2D systolic
Distributed Arithmetic (DA) based structures that are designed
for the implementation of Finite Impulse Response (FIR) filters.
The paper compares the 1D DA based systolic structure with
1D systolic DA based decomposition method. The filters are
implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using
HDL and system metrics like Area, Gate Count, Maximum
Usable Frequency and Power consumption are estimated for
different filter orders and address lengths. The 1D systolic
decomposition structure is also compared with the existing
system generator implementation of DA FIR.. Results for an
exemplary implementation are presented.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Computational Engineering Research(IJCER)ijceronline
This document summarizes a research paper on designing a high-speed arithmetic architecture for a parallel multiplier-accumulator based on the radix-2 modified Booth algorithm. It presents the design of a modified Booth multiplier using a carry lookahead adder for high accuracy with a fixed width. It also proposes a high-speed MAC architecture that improves performance by eliminating the accumulator and modifying the carry-save adder to add lower bits in advance, reducing the number of inputs to the final adder. The proposed CSA architecture can efficiently implement the operations of the new MAC arithmetic.
IRJET- Efficient Shift add Implementation of Fir Filter using Variable Pa...IRJET Journal
This document discusses efficient implementations of shift-add operations in finite impulse response (FIR) filters using variable partition hybrid form structures. FIR filters are widely used in digital signal processing and their performance is dominated by multiplication operations. The proposed method aims to reduce power consumption and complexity by implementing multiplications using optimized shift-add networks instead of multipliers. It explores variable size partitioning approaches and prefix adders to reduce gate count, dynamic power, and improve filter performance.
This project describes a novel architecture based on Recursive Running Sum (RRS) filter implementation for wire and wireless data processing. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one tenth of required bit period. The intermediate data bit is decoded using magnitude comparator. The advantage of this architecture is that baud rate is decided by the window size so there is no need of any external “timer module” which is normally required for standard UARTs. The Recursive Running Sum (RRS) filter architecture with programmable window size of M is designed and modules are implemented with VHDL language. This project implementation includes many applications in wireless data communication Systems like RF, Blue tooth, WIFI, ZigBee wireless sensor applications. Total coding written in VHDL language. Simulation in Modelsim Simulator, Synthesis done by XILINX ISE 9.2i. Synthesis result is verified by the Chipscope. Input signal given from the keyboard and output is seen by the help of HyperTerminal.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Design of Area Efficient Digital FIR Filter using MACIRJET Journal
This document describes the design of an area efficient digital FIR filter using a single MAC (multiply-accumulate) unit. It begins with an introduction to digital filters and FIR filters. It then discusses related work on optimizing FIR filter design through techniques like coefficient quantization and constant multiplication. The proposed methodology involves specifying the FIR filter, generating coefficients by rounding to integers, and designing the filter architecture using a single MAC unit, multiplexers, and other components. This approach aims to reduce area by avoiding two's complement circuits and using a single MAC unit instead of multiple parallel multipliers. The document concludes the proposed work provides a good direction for optimizing the area of digital filters.
Design and Implementation of a Programmable Truncated Multiplierijsrd.com
Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. However, this result in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction trade off against signal degradation which can be modified at run time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analysed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation also shown to be effective when deploying truncated multipliers in a system.
The document discusses implementing convolution on an FPGA. It begins by introducing convolution and its applications in image processing. It then discusses the scope and technical approach of implementing discrete linear convolution on FPGA kits in order to perform convolution on images in real-time. The document outlines the structure of FPGAs, including configurable logic blocks and wiring tracks. It also discusses software requirements and provides an organization plan for subsequent chapters on linear convolution, FPGA technology, and a literature survey.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
This document analyzes various multiple constant multiplication (MCM) algorithms for implementing reconfigurable root raised cosine (RRC) finite impulse response (FIR) filters. It compares digit based recoding, canonic sign digit (CSD), common subexpression elimination (CSE), and binary common subexpression elimination (BCSE) algorithms in terms of area, power, and speed. The results show that the BCSE algorithm provides the best performance, reducing area by up to 11.7% and power consumption compared to the other methods. The BCSE technique reuses common binary bit patterns within filter coefficients to optimize constant multiplications.
1. The document presents a design for a modified Booth recoder using a fused add-multiply (FAM) operator to implement digital signal processing applications more efficiently.
2. It proposes a new recoding technique to decrease the critical path delay and reduce area and power consumption of the FAM unit compared to existing recoding schemes.
3. The technique is also applied to the implementation of finite impulse response (FIR) filters to further optimize hardware usage and achieve faithfully rounded outputs within tight area and power constraints for mobile applications.
Design and Implementation of Low Power DSP Core with Programmable Truncated V...ijsrd.com
The programmable truncated Vedic multiplication is the method which uses Vedic multiplier and programmable truncation control bits and which reduces part of the area and power required by multipliers by only computing the most-significant bits of the product. The basic process of truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. These results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision vedic multiplier is implemented, but the active section of the truncation is selected by truncation control bits dynamically at run-time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a high speed Vedic truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. On comparison with the previous parallel multipliers Vedic should be much more fast and area should be reduced. Programmable truncated Vedic multiplier (PTVM) should be the basic part implemented for the arithmetic and PTMAC units.
Design and implementation of different audio restoration techniques for audio...eSAT Journals
This document summarizes research on designing and implementing different audio restoration techniques for removing distortions like clipping, clicks, and broadband noise from audio signals. It presents methods for declipping audio using sparse representations and frame-based reconstruction. Clicks are addressed using an adaptive filtering method, and broadband noise is reduced via spectral subtraction. The performance of these techniques is evaluated using metrics like SNR and algorithms like OMP. Hardware implementation of click removal is done on a TMS320C6713 DSK board using tools like MATLAB and Code Composer Studio.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document describes a proposed VLSI architecture for an optimized low power digit serial finite impulse response (FIR) filter using multiple constant multiplications (MCM). It introduces an algorithm to optimize the area of digit serial MCM operations at the gate level by considering implementation costs of digit serial addition, subtraction, and shift operations. The proposed filter architecture aims to reduce area and power compared to designs using generic digit serial multipliers through the use of MCM blocks optimized for area. Experimental results indicate the algorithm leads to lower complexity digit serial MCM designs.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
The document describes an efficient hardware co-simulation approach for designing a digital down converter (DDC) for software defined radios. The proposed DDC uses optimal equiripple techniques to reduce resource requirements. It employs a computationally efficient polyphase decomposition structure to improve hardware complexity. The DDC is implemented using embedded multipliers, lookup tables, and block RAMs of a Virtex-II Pro FPGA. Simulation results show the DDC can operate at 160 MHz while consuming 0.34004W. It utilizes few FPGA resources, providing a cost-effective solution for software defined radio applications.
An fpga implementation of the lms adaptive filter eSAT Journals
This document describes an FPGA implementation of the Least Mean Square (LMS) adaptive filter algorithm for active vibration control. It compares fixed-point and floating-point implementations in terms of area usage and performance. The LMS algorithm is implemented using a finite state machine model with separate modules for operations like filtering, error estimation, and weight adaptation. Both implementations utilize this structural model. The fixed-point version uses 16-bit integers and fractions, while the floating-point version leverages IP cores. Results show the floating-point implementation has better accuracy and resource utilization than the fixed-point version for active vibration control applications on FPGAs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
This document summarizes a research paper that proposes an efficient VLSI implementation of a pipelined fast Fourier transform (FFT). The key aspects are:
1) A single-path delay feedback (SDF) pipeline architecture is adopted to implement the FFT processor. This architecture requires less memory space and has lower power consumption than existing designs.
2) A reconfigurable complex multiplier and bit-parallel multipliers are used instead of read-only memories to store twiddle factors. This eliminates the need for ROMs and reduces power consumption.
3) The proposed FFT architecture contains three types of processing elements - a complex constant multiplier, delay buffers, and extra units for IFFT computation. It achieves a
FIR Filter Implementation by Systolization using DA-based DecompositionIDES Editor
In this paper we present 1D and 2D systolic
Distributed Arithmetic (DA) based structures that are designed
for the implementation of Finite Impulse Response (FIR) filters.
The paper compares the 1D DA based systolic structure with
1D systolic DA based decomposition method. The filters are
implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using
HDL and system metrics like Area, Gate Count, Maximum
Usable Frequency and Power consumption are estimated for
different filter orders and address lengths. The 1D systolic
decomposition structure is also compared with the existing
system generator implementation of DA FIR.. Results for an
exemplary implementation are presented.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Computational Engineering Research(IJCER)ijceronline
This document summarizes a research paper on designing a high-speed arithmetic architecture for a parallel multiplier-accumulator based on the radix-2 modified Booth algorithm. It presents the design of a modified Booth multiplier using a carry lookahead adder for high accuracy with a fixed width. It also proposes a high-speed MAC architecture that improves performance by eliminating the accumulator and modifying the carry-save adder to add lower bits in advance, reducing the number of inputs to the final adder. The proposed CSA architecture can efficiently implement the operations of the new MAC arithmetic.
IRJET- Efficient Shift add Implementation of Fir Filter using Variable Pa...IRJET Journal
This document discusses efficient implementations of shift-add operations in finite impulse response (FIR) filters using variable partition hybrid form structures. FIR filters are widely used in digital signal processing and their performance is dominated by multiplication operations. The proposed method aims to reduce power consumption and complexity by implementing multiplications using optimized shift-add networks instead of multipliers. It explores variable size partitioning approaches and prefix adders to reduce gate count, dynamic power, and improve filter performance.
This project describes a novel architecture based on Recursive Running Sum (RRS) filter implementation for wire and wireless data processing. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one tenth of required bit period. The intermediate data bit is decoded using magnitude comparator. The advantage of this architecture is that baud rate is decided by the window size so there is no need of any external “timer module” which is normally required for standard UARTs. The Recursive Running Sum (RRS) filter architecture with programmable window size of M is designed and modules are implemented with VHDL language. This project implementation includes many applications in wireless data communication Systems like RF, Blue tooth, WIFI, ZigBee wireless sensor applications. Total coding written in VHDL language. Simulation in Modelsim Simulator, Synthesis done by XILINX ISE 9.2i. Synthesis result is verified by the Chipscope. Input signal given from the keyboard and output is seen by the help of HyperTerminal.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Design of Area Efficient Digital FIR Filter using MACIRJET Journal
This document describes the design of an area efficient digital FIR filter using a single MAC (multiply-accumulate) unit. It begins with an introduction to digital filters and FIR filters. It then discusses related work on optimizing FIR filter design through techniques like coefficient quantization and constant multiplication. The proposed methodology involves specifying the FIR filter, generating coefficients by rounding to integers, and designing the filter architecture using a single MAC unit, multiplexers, and other components. This approach aims to reduce area by avoiding two's complement circuits and using a single MAC unit instead of multiple parallel multipliers. The document concludes the proposed work provides a good direction for optimizing the area of digital filters.
Design and Implementation of a Programmable Truncated Multiplierijsrd.com
Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. However, this result in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction trade off against signal degradation which can be modified at run time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analysed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation also shown to be effective when deploying truncated multipliers in a system.
The document discusses implementing convolution on an FPGA. It begins by introducing convolution and its applications in image processing. It then discusses the scope and technical approach of implementing discrete linear convolution on FPGA kits in order to perform convolution on images in real-time. The document outlines the structure of FPGAs, including configurable logic blocks and wiring tracks. It also discusses software requirements and provides an organization plan for subsequent chapters on linear convolution, FPGA technology, and a literature survey.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
This document analyzes various multiple constant multiplication (MCM) algorithms for implementing reconfigurable root raised cosine (RRC) finite impulse response (FIR) filters. It compares digit based recoding, canonic sign digit (CSD), common subexpression elimination (CSE), and binary common subexpression elimination (BCSE) algorithms in terms of area, power, and speed. The results show that the BCSE algorithm provides the best performance, reducing area by up to 11.7% and power consumption compared to the other methods. The BCSE technique reuses common binary bit patterns within filter coefficients to optimize constant multiplications.
1. The document presents a design for a modified Booth recoder using a fused add-multiply (FAM) operator to implement digital signal processing applications more efficiently.
2. It proposes a new recoding technique to decrease the critical path delay and reduce area and power consumption of the FAM unit compared to existing recoding schemes.
3. The technique is also applied to the implementation of finite impulse response (FIR) filters to further optimize hardware usage and achieve faithfully rounded outputs within tight area and power constraints for mobile applications.
Design and Implementation of Low Power DSP Core with Programmable Truncated V...ijsrd.com
The programmable truncated Vedic multiplication is the method which uses Vedic multiplier and programmable truncation control bits and which reduces part of the area and power required by multipliers by only computing the most-significant bits of the product. The basic process of truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. These results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision vedic multiplier is implemented, but the active section of the truncation is selected by truncation control bits dynamically at run-time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a high speed Vedic truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. On comparison with the previous parallel multipliers Vedic should be much more fast and area should be reduced. Programmable truncated Vedic multiplier (PTVM) should be the basic part implemented for the arithmetic and PTMAC units.
Design and implementation of different audio restoration techniques for audio...eSAT Journals
This document summarizes research on designing and implementing different audio restoration techniques for removing distortions like clipping, clicks, and broadband noise from audio signals. It presents methods for declipping audio using sparse representations and frame-based reconstruction. Clicks are addressed using an adaptive filtering method, and broadband noise is reduced via spectral subtraction. The performance of these techniques is evaluated using metrics like SNR and algorithms like OMP. Hardware implementation of click removal is done on a TMS320C6713 DSK board using tools like MATLAB and Code Composer Studio.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document describes a proposed VLSI architecture for an optimized low power digit serial finite impulse response (FIR) filter using multiple constant multiplications (MCM). It introduces an algorithm to optimize the area of digit serial MCM operations at the gate level by considering implementation costs of digit serial addition, subtraction, and shift operations. The proposed filter architecture aims to reduce area and power compared to designs using generic digit serial multipliers through the use of MCM blocks optimized for area. Experimental results indicate the algorithm leads to lower complexity digit serial MCM designs.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
The document describes an efficient hardware co-simulation approach for designing a digital down converter (DDC) for software defined radios. The proposed DDC uses optimal equiripple techniques to reduce resource requirements. It employs a computationally efficient polyphase decomposition structure to improve hardware complexity. The DDC is implemented using embedded multipliers, lookup tables, and block RAMs of a Virtex-II Pro FPGA. Simulation results show the DDC can operate at 160 MHz while consuming 0.34004W. It utilizes few FPGA resources, providing a cost-effective solution for software defined radio applications.
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
The document describes the design and implementation of an efficient digital down converter (DDC) for software defined radios. The proposed DDC uses optimal equiripple techniques to reduce resource requirements. It employs a computationally efficient polyphase decomposition structure to improve hardware complexity. The DDC is implemented using embedded multipliers, lookup tables, and block RAMs of a Virtex-II Pro FPGA. Simulation results show the DDC can operate at 160 MHz while consuming 0.34004W. Implementation requires few FPGA resources, providing a low-cost solution for software defined radio applications.
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
IRJET- A Digital Down Converter on Zynq SoCIRJET Journal
This document describes the design and implementation of a digital down converter (DDC) on a Zynq System on Chip (SoC). Key points:
- The DDC is designed for airborne radar receivers to downconvert high sample rate digitized signals to a lower frequency for easier processing.
- The DDC implementation includes a direct digital synthesizer to generate input signals, complex multiplication for mixing, and a two-stage decimation and filtering process.
- The design is implemented on a Zynq SoC which provides the flexibility of a processor and programmability of an FPGA.
- Results show the DDC design achieves significant improvements in resource utilization compared to a full
The Boolean expression at TP1 with respect to the corresponding inputs is:
TP1 = A + B
Question 2.
Question :
(TCO 3) Determine the Boolean expression at TP2 with respect to the corresponding inputs.
Student Answer:
TP2 = C
Instructor Explanation:
Correct. TP2 is simply the input C, so the Boolean expression is C.
Question 3.
Question :
(TCO 3) Determine the Boolean expression at TP3 with respect to the corresponding inputs.
Student Answer:
TP3 = A·C + B
Instructor Explanation:
Correct. TP3 is the output of an AND gate (A and C
Iaetsd pipelined parallel fft architecture through folding transformationIaetsd Iaetsd
This document presents a new VLSI architecture for a real-time pipeline FFT processor using fused floating point operations. It proposes high radix floating point butterflies implemented with two fused operations: a two-term dot product and add-subtract unit. Both discrete and fused radix processors are compared in terms of area. Higher throughput is achieved using a proposed architecture with conflict-free memory access and a new addressing scheme for radix-16 FFT.
Basic signal processing system design on fpga using lms based adaptive filtereSAT Journals
Abstract
Adaptive digital filter based on LMS algorithms widely used in the area of digital signal processing to iteratively estimate the
statistics of an unknown signal. Design of an adaptive filter is based on three major computing elements namely multiplier, adder
and delay unit torealize the Finite Impulse Response (FIR) filter. The filter weights( coefficient) of the FIR filter are adjusted
automatically by Least Mean Square of the error so as to match the adapted output to the desired input. This paper explains the
design of adaptive filter by two approaches. One is model based approach and other is Field Programmable Gate Arrays
(FPGAs). The model based design approach is developed around MATLAB, SIMULINK and SYSTEM GENERATOR tools, which
provide a virtual FPGA platform. Modern FPGA include the resources needed to design efficient filtering structures. The LMS
algorithm has been implemented on CYCLONE II EP2C35F672C8 FPGA device, using ALTERA QUARTUS II development
platform. The three major demonstrable applications cited in the present work are System Identification, Noise reduction and
Echo cancellation.
Keywords – Signal Processing; FPGA; Adaptive Filter; DE2KIT
A prototyping of software defined radio using qpsk modulationIAEME Publication
This document summarizes a student thesis on prototyping a software defined radio using QPSK modulation. The design includes a digital up converter (DUC) for transmission and a digital down converter (DDC) for reception. The DUC uses pulse shaping FIR filters, compensating FIR filters, and cascaded integrator comb filters to upconvert the baseband signal to an intermediate frequency. QPSK is used for both modulation and demodulation. The system is simulated and implemented on an FPGA, with results showing the simulation and experimental results are similar.
Modified Distributive Arithmetic Based DWT-IDWT Processor Design and FPGA Imp...IOSR Journals
1) The document describes a modified distributive arithmetic based discrete wavelet transform (DWT) processor architecture and its FPGA implementation for image compression.
2) The proposed architecture uses four lookup tables to store pre-computed partial products of filter coefficients, achieving a latency of 44 clock cycles and throughput of 4 clock cycles.
3) A software reference model is developed in Matlab to analyze the performance of various wavelets for image compression using the distributive arithmetic based DWT approach. The input image is resized and decomposed into sub-bands using DWT and reconstructed using IDWT.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document discusses the design and analysis of multirate filters for WiMAX applications. It proposes a programmable multirate filter architecture that can be implemented using software-defined radio technology and multirate signal processing principles. The filters are designed using MATLAB's filter design and analysis tool to meet WiMAX specifications. A digital upconverter is presented that uses three cascaded FIR filters with interpolation factors of 1, 2, and 4 to achieve an overall interpolation factor of 8 as required by WiMAX. The filters are analyzed and simulated in MATLAB to verify they satisfy WiMAX's spectral mask requirements.
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
FPGA Implementation of Optimized CIC Filter for Sample Rate Conversion in Sof...idescitation
A software radio receiver is one which is tuned to
receive a transmitted signal on multiple communication
standards through software rather than hardware. To
incorporate multi-standard radio communications an
intermediate frequency of high ranges is used. Such high
intermediate frequencies when sampled with Nyquist rate
gets oversampled due to the phenomenon of Band Pass
sampling depending on the radio communication standard.
Hence a digital down converter (DDC) capable of reducing
the sampling rate in accordance with the radio communication
standard is required. Cascaded Integrated Comb (CIC) filters
are used for large sample rate conversion factors. In this paper
an optimized architecture for DDC employing CORDIC in
the mixer stage and the reconfigurable decimation factors for
CIC filters has been implemented. Optimized implementation
of CIC filter for sample rate conversion of multi-standard
radio communications reduces the hardware resources by more
than twenty percent when compared with the non-optimized
architecture.
CANONIC SIGNED DIGIT BASED DESIGN OF MULTIPLIER-LESS FIR FILTER USING SELFORG...ijaia
This document summarizes a research paper that proposes a design for multiplier-less finite impulse response (FIR) filters using the Self-organizing Random Immigrants Genetic Algorithm (SORIGA). FIR filter coefficients can be represented in binary or Canonic Signed Digit (CSD) number systems to reduce hardware costs by eliminating multipliers. The paper describes these number system representations and the SORIGA technique is used to optimize the coefficients to minimize hardware costs while maintaining filter performance. Simulation results are presented and hardware costs of the designed filter are analyzed and compared to other existing designs.
This document summarizes a paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a low complexity turbo decoder architecture using a modified Add Compare Select (ACS) unit and registers to implement the Constant log BCJR algorithm. The Constant log BCJR algorithm reduces complexity compared to other MAP decoding algorithms. The proposed decoder is designed to decode two blocks of data simultaneously, increasing throughput. Simulation and synthesis results showed the Constant log BCJR decoder uses less memory and power than an LUT log BCJR decoder.
Similar to FPGA based Efficient Interpolator design using DALUT Algorithm (20)
ANALYSIS OF LAND SURFACE DEFORMATION GRADIENT BY DINSAR cscpconf
The progressive development of Synthetic Aperture Radar (SAR) systems diversify the exploitation of the generated images by these systems in different applications of geoscience. Detection and monitoring surface deformations, procreated by various phenomena had benefited from this evolution and had been realized by interferometry (InSAR) and differential interferometry (DInSAR) techniques. Nevertheless, spatial and temporal decorrelations of the interferometric couples used, limit strongly the precision of analysis results by these techniques. In this context, we propose, in this work, a methodological approach of surface deformation detection and analysis by differential interferograms to show the limits of this technique according to noise quality and level. The detectability model is generated from the deformation signatures, by simulating a linear fault merged to the images couples of ERS1 / ERS2 sensors acquired in a region of the Algerian south.
4D AUTOMATIC LIP-READING FOR SPEAKER'S FACE IDENTIFCATIONcscpconf
A novel based a trajectory-guided, concatenating approach for synthesizing high-quality image real sample renders video is proposed . The lips reading automated is seeking for modeled the closest real image sample sequence preserve in the library under the data video to the HMM predicted trajectory. The object trajectory is modeled obtained by projecting the face patterns into an KDA feature space is estimated. The approach for speaker's face identification by using synthesise the identity surface of a subject face from a small sample of patterns which sparsely each the view sphere. An KDA algorithm use to the Lip-reading image is discrimination, after that work consisted of in the low dimensional for the fundamental lip features vector is reduced by using the 2D-DCT.The mouth of the set area dimensionality is ordered by a normally reduction base on the PCA to obtain the Eigen lips approach, their proposed approach by[33]. The subjective performance results of the cost function under the automatic lips reading modeled , which wasn’t illustrate the superior performance of the
method.
MOVING FROM WATERFALL TO AGILE PROCESS IN SOFTWARE ENGINEERING CAPSTONE PROJE...cscpconf
Universities offer software engineering capstone course to simulate a real world-working environment in which students can work in a team for a fixed period to deliver a quality product. The objective of the paper is to report on our experience in moving from Waterfall process to Agile process in conducting the software engineering capstone project. We present the capstone course designs for both Waterfall driven and Agile driven methodologies that highlight the structure, deliverables and assessment plans.To evaluate the improvement, we conducted a survey for two different sections taught by two different instructors to evaluate students’ experience in moving from traditional Waterfall model to Agile like process. Twentyeight students filled the survey. The survey consisted of eight multiple-choice questions and an open-ended question to collect feedback from students. The survey results show that students were able to attain hands one experience, which simulate a real world-working environment. The results also show that the Agile approach helped students to have overall better design and avoid mistakes they have made in the initial design completed in of the first phase of the capstone project. In addition, they were able to decide on their team capabilities, training needs and thus learn the required technologies earlier which is reflected on the final product quality
PROMOTING STUDENT ENGAGEMENT USING SOCIAL MEDIA TECHNOLOGIEScscpconf
This document discusses using social media technologies to promote student engagement in a software project management course. It describes the course and objectives of enhancing communication. It discusses using Facebook for 4 years, then switching to WhatsApp based on student feedback, and finally introducing Slack to enable personalized team communication. Surveys found students engaged and satisfied with all three tools, though less familiar with Slack. The conclusion is that social media promotes engagement but familiarity with the tool also impacts satisfaction.
A SURVEY ON QUESTION ANSWERING SYSTEMS: THE ADVANCES OF FUZZY LOGICcscpconf
In real world computing environment with using a computer to answer questions has been a human dream since the beginning of the digital era, Question-answering systems are referred to as intelligent systems, that can be used to provide responses for the questions being asked by the user based on certain facts or rules stored in the knowledge base it can generate answers of questions asked in natural , and the first main idea of fuzzy logic was to working on the problem of computer understanding of natural language, so this survey paper provides an overview on what Question-Answering is and its system architecture and the possible relationship and
different with fuzzy logic, as well as the previous related research with respect to approaches that were followed. At the end, the survey provides an analytical discussion of the proposed QA models, along or combined with fuzzy logic and their main contributions and limitations.
DYNAMIC PHONE WARPING – A METHOD TO MEASURE THE DISTANCE BETWEEN PRONUNCIATIONS cscpconf
Human beings generate different speech waveforms while speaking the same word at different times. Also, different human beings have different accents and generate significantly varying speech waveforms for the same word. There is a need to measure the distances between various words which facilitate preparation of pronunciation dictionaries. A new algorithm called Dynamic Phone Warping (DPW) is presented in this paper. It uses dynamic programming technique for global alignment and shortest distance measurements. The DPW algorithm can be used to enhance the pronunciation dictionaries of the well-known languages like English or to build pronunciation dictionaries to the less known sparse languages. The precision measurement experiments show 88.9% accuracy.
INTELLIGENT ELECTRONIC ASSESSMENT FOR SUBJECTIVE EXAMS cscpconf
In education, the use of electronic (E) examination systems is not a novel idea, as Eexamination systems have been used to conduct objective assessments for the last few years. This research deals with randomly designed E-examinations and proposes an E-assessment system that can be used for subjective questions. This system assesses answers to subjective questions by finding a matching ratio for the keywords in instructor and student answers. The matching ratio is achieved based on semantic and document similarity. The assessment system is composed of four modules: preprocessing, keyword expansion, matching, and grading. A survey and case study were used in the research design to validate the proposed system. The examination assessment system will help instructors to save time, costs, and resources, while increasing efficiency and improving the productivity of exam setting and assessments.
TWO DISCRETE BINARY VERSIONS OF AFRICAN BUFFALO OPTIMIZATION METAHEURISTICcscpconf
African Buffalo Optimization (ABO) is one of the most recent swarms intelligence based metaheuristics. ABO algorithm is inspired by the buffalo’s behavior and lifestyle. Unfortunately, the standard ABO algorithm is proposed only for continuous optimization problems. In this paper, the authors propose two discrete binary ABO algorithms to deal with binary optimization problems. In the first version (called SBABO) they use the sigmoid function and probability model to generate binary solutions. In the second version (called LBABO) they use some logical operator to operate the binary solutions. Computational results on two knapsack problems (KP and MKP) instances show the effectiveness of the proposed algorithm and their ability to achieve good and promising solutions.
DETECTION OF ALGORITHMICALLY GENERATED MALICIOUS DOMAINcscpconf
In recent years, many malware writers have relied on Dynamic Domain Name Services (DDNS) to maintain their Command and Control (C&C) network infrastructure to ensure a persistence presence on a compromised host. Amongst the various DDNS techniques, Domain Generation Algorithm (DGA) is often perceived as the most difficult to detect using traditional methods. This paper presents an approach for detecting DGA using frequency analysis of the character distribution and the weighted scores of the domain names. The approach’s feasibility is demonstrated using a range of legitimate domains and a number of malicious algorithmicallygenerated domain names. Findings from this study show that domain names made up of English characters “a-z” achieving a weighted score of < 45 are often associated with DGA. When a weighted score of < 45 is applied to the Alexa one million list of domain names, only 15% of the domain names were treated as non-human generated.
GLOBAL MUSIC ASSET ASSURANCE DIGITAL CURRENCY: A DRM SOLUTION FOR STREAMING C...cscpconf
The document proposes a blockchain-based digital currency and streaming platform called GoMAA to address issues of piracy in the online music streaming industry. Key points:
- GoMAA would use a digital token on the iMediaStreams blockchain to enable secure dissemination and tracking of streamed content. Content owners could control access and track consumption of released content.
- Original media files would be converted to a Secure Portable Streaming (SPS) format, embedding watermarks and smart contract data to indicate ownership and enable validation on the blockchain.
- A browser plugin would provide wallets for fans to collect GoMAA tokens as rewards for consuming content, incentivizing participation and addressing royalty discrepancies by recording
IMPORTANCE OF VERB SUFFIX MAPPING IN DISCOURSE TRANSLATION SYSTEMcscpconf
This document discusses the importance of verb suffix mapping in discourse translation from English to Telugu. It explains that after anaphora resolution, the verbs must be changed to agree with the gender, number, and person features of the subject or anaphoric pronoun. Verbs in Telugu inflect based on these features, while verbs in English only inflect based on number and person. Several examples are provided that demonstrate how the Telugu verb changes based on whether the subject or pronoun is masculine, feminine, neuter, singular or plural. Proper verb suffix mapping is essential for generating natural and coherent translations while preserving the context and meaning of the original discourse.
EXACT SOLUTIONS OF A FAMILY OF HIGHER-DIMENSIONAL SPACE-TIME FRACTIONAL KDV-T...cscpconf
In this paper, based on the definition of conformable fractional derivative, the functional
variable method (FVM) is proposed to seek the exact traveling wave solutions of two higherdimensional
space-time fractional KdV-type equations in mathematical physics, namely the
(3+1)-dimensional space–time fractional Zakharov-Kuznetsov (ZK) equation and the (2+1)-
dimensional space–time fractional Generalized Zakharov-Kuznetsov-Benjamin-Bona-Mahony
(GZK-BBM) equation. Some new solutions are procured and depicted. These solutions, which
contain kink-shaped, singular kink, bell-shaped soliton, singular soliton and periodic wave
solutions, have many potential applications in mathematical physics and engineering. The
simplicity and reliability of the proposed method is verified.
AUTOMATED PENETRATION TESTING: AN OVERVIEWcscpconf
The document discusses automated penetration testing and provides an overview. It compares manual and automated penetration testing, noting that automated testing allows for faster, more standardized and repeatable tests but has limitations in developing new exploits. It also reviews some current automated penetration testing methodologies and tools, including those using HTTP/TCP/IP attacks, linking common scanning tools, a Python-based tool targeting databases, and one using POMDPs for multi-step penetration test planning under uncertainty. The document concludes that automated testing is more efficient than manual for known vulnerabilities but cannot replace manual testing for discovering new exploits.
CLASSIFICATION OF ALZHEIMER USING fMRI DATA AND BRAIN NETWORKcscpconf
Since the mid of 1990s, functional connectivity study using fMRI (fcMRI) has drawn increasing
attention of neuroscientists and computer scientists, since it opens a new window to explore
functional network of human brain with relatively high resolution. BOLD technique provides
almost accurate state of brain. Past researches prove that neuro diseases damage the brain
network interaction, protein- protein interaction and gene-gene interaction. A number of
neurological research paper also analyse the relationship among damaged part. By
computational method especially machine learning technique we can show such classifications.
In this paper we used OASIS fMRI dataset affected with Alzheimer’s disease and normal
patient’s dataset. After proper processing the fMRI data we use the processed data to form
classifier models using SVM (Support Vector Machine), KNN (K- nearest neighbour) & Naïve
Bayes. We also compare the accuracy of our proposed method with existing methods. In future,
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2. 52 Computer Science & Information Technology (CS & IT)
The applications of digital FIR filter and up/down sampling techniques are found everywhere in
modem electronic products. For every electronic product, lower circuit complexity is always an
important design target since it reduces the cost. There are many applications where the sampling
rate must be changed. Interpolators and decimators are utilized to increase or decrease the
sampling rate. Up sampler and down sampler are used to change the sampling rate of digital
signal in multi rate DSP systems [1]. This rate conversion requirement leads to production of
undesired signals associated with aliasing and imaging errors. So some kind of filter should be
placed to attenuate these errors
Today’s consumer electronics such as cellular phones and other multi-media and wireless devices
often require multirate digital signal processing (DSP) algorithms for several crucial operations in
order to increase speed, reduce area and power consumption. Due to a growing demand for such
complex DSP applications, high performance, low-cost Soc implementations of DSP algorithms
are receiving increased attention among researchers and design engineers [2]. Although ASICs
and DSP chips have been the traditional solution for high performance applications, now the
technology and the market demands are looking for changes. On one hand, high development
costs and time-to-market factors associated with ASICs can be prohibitive for certain applications
while, on the other hand, programmable DSP processors can be unable to meet desired
performance due to their sequential execution architecture. In this context, embedded FPGAs
offer a very attractive solution that balance high flexibility, time-to-market, cost and
performance. Therefore, in this paper, an interpolator is designed and implemented on FPGA
device. An impulse response of an FIR filter may be expressed as:
(1)
where C1,C2…….CK are fixed coefficients and the x1, x2……… xK are the input data words. A
typical digital implementation will require K multiply-and-accumulate (MAC) operations, which
are expensive to compute in hardware due to logic complexity, area usage, and throughput.
Alternatively, the MAC operations may be replaced by a series of look-up-table (LUT) accesses
and summations. Such an implementation of the filter is known as distributed arithmetic (DA).
2 Interpolator
In multirate systems, up sampler is basic sampling rate alteration device used to increase the
sampling rate by an integer factor. An up sampler with an up-sampling factor L, where L is a
positive integer, develops an output sequence xu[n] with a sampling rate that is L times larger
than that of the input sequence x[n] . The up sampler is shown in Fig1
k
K
k
k XCY ∑=
=
1
3. Computer Science & Information Technology (CS & IT) 53
Figure1. Up Sampler
Up-sampling operation is implemented by inserting L-1 equidistant zero-valued samples
between two consecutive samples of x[n]. The input and output relation of up sampler
can be expressed as
Xu[n]= ቄ
xሾn/Lሿ, n ൌ 0, േL, േ2L ….
0 ݁ݏ݅ݓݎ݄݁ݐ
(2)
The zero-valued samples inserted by the up-sampler are replaced with appropriate nonzero values
using some type of filtering process called interpolation [3]. The input-output relation of an up-
sampler with factor of 2 in the time-domain is given by:
(3)
The z transform of input output relation is given by
(4)
=X(Z2
) (5)
In a similar manner, we can show that for a factor-of-L up-sampler
Xu(Z)=X(ZL
) (6)
On the unit circle, for z =e jω
, input-output relation is given by
Xu(ejω
)=X(ejωL
) (7)
A factor-of-2 sampling rate expansion leads to a compression of X(ejω
) by a factor of 2 and a 2-
fold repetition in the baseband [0, 2π].This process is called imaging as we get an additional
“image” of the input spectrum. Similarly in the case of a factor of-L sampling rate expansion,
[ ]
±±=
=
otherwise
nnx
nxu
,0
4,22/
][
L
∑
∞
−∞=
−
=
n
n
uu ZnxZX ][)( n
n
znx −
∞
−∞=
= ∑,
]2/[
∑
∞
−∞=
−
=
m
m
zmx 2
][
4. 54 Computer Science & Information Technology (CS & IT)
there will be L-1 additional images of the input spectrum in the baseband. Interpolator is used as
low pass filter to remove the xu[n] images and in effect “fills in” the zero-valued samples in xu[n]
with interpolated sample values [4]-[6].
3 Distributed Arithmetic Algorithm
In the recent years, there has been a growing trend to implement digital signal processing
functions in Field Programmable Gate Array (FPGA). Distributed Arithmetic (DA) appeared as a
very efficient solution especially suited for LUT-based FPGA architectures. This technique, first
proposed by Croisier is a multiplier-less architecture that is based on an efficient partition of the
function in partial terms using 2’s complement binary representation of data. The partial terms
can be pre-computed and stored in LUTs. The flexibility of this algorithm on FPGAs permits
everything from bit-serial implementations to pipelined or full-parallel versions of the scheme,
which can greatly improve the design performance [7]
The multiplier less distributed arithmetic (DA)-based technique has gained substantial popularity,
Due to its high-throughput processing capability and increased regularity, results in cost-effective
and area-time efficient computing structures. The main operations required for DA-based
computation of inner product are a sequence of lookup table (LUT) accesses followed by shift-
accumulation operations of the LUT output. DA-based computation is well suited for FPGA
realization, because the LUT as well as the shift-add operations, can be efficiently mapped to the
LUT-based FPGA logic structures.[8]
Multiplier-less schemes can be classified in two categories according to how they manipulate the
filter coefficients for the multiply operation. In first type of multiplier-less technique, the
coefficients are transformed to other numeric representations whose hardware implementation or
manipulation is more efficient than the traditional binary representation such as Canonic Sign
Digit (CSD) method, in which coefficients are represented by a combination of powers of two in
such a way that multiplication can be simply implemented with adder/subtractors and shifters [9]
The second type of multiplier-less method involves the use of memories (RAMs, ROMs) or
Look-Up Tables (LUTs) to store pre-computed values of coefficient operations.
In FIR filtering, one of the convolving sequences is derived from the input samples while the
other sequence is derived from the fixed impulse response coefficients of the filter. This behavior
of the FIR filter makes it possible to use DA-based technique for memory-based realization. It
yields faster output compared with the multiplier-accumulator-based designs because it stores the
pre computed partial results in the memory elements, which can be read out and accumulated to
obtain the desired result. The memory requirement of DA-based implementation for FIR filters,
however, increases exponentially with the filter order.
5. Computer Science & Information Technology (CS & IT) 55
DISTRIBUTED ARITHMETIC (DA) is computation algorithm that performs multiplication with
look-up table based schemes. DA specifically targets the sum of products (sometimes referred to
as the vector dot product) computation that covers many of the important DSP filtering and
frequency transforming functions. It uses look-up tables and accumulators instead of multipliers
for computing inner products and has been widely used in many DSP applications such as DFT,
DCT, convolution, and digital filters [10]. The example of direct DA inner-product generation is
shown in Eq. (1) where xk is a 2's-complement binary number scaled such that |xk| < 1. We may
express each xk as
(8)
where the bkn are the bits, 0 or 1, bk0 is the sign bit. Now combining Eq. (1) and (8) in order to
express y in terms of the bits of xk; we see
(9)
The above Eq. (9) is the conventional form of expressing the inner product. Interchanging the
order of the summations, gives us:
(10)
Eq.(10) shows a DA computation where the bracketed term is given by
(11)
Each bkn can have values of 0 and 1 so Eq.(11) can have 2K possible values. Rather than
computing these values on line, we may pre-compute the values and store them in a ROM. The
input data can be used to directly address the memory and the result. After N such cycles, the
memory contains the result, y. The term xk may be written as
Xk = ½{xk-(-xk)} (12)
and in 2's-complement notation the negative of xk may be written as:
n
N
n
knkk bbx −
−
=
∑+−= 2
1
1
0
]2[
1
11
∑∑
−
=
−
=
+−=
N
n
n
kn
K
k
kk bbCY
)(2][ 0
11
1
1
k
k
k
k
K
k
n
knk
N
n
bcbCY −+= ∑∑∑ ==
−
−
=
kn
K
k
k bC∑=1
6. 56 Computer Science & Information Technology (CS & IT)
(13)
where the over score symbol indicates the complement of a bit. By substituting Eq.(8) & (13) into
Eq.(12), we get
(14)
In order to simplify the notation later, it is
convenient to define the new variables as
For n്0 (15)
And (16)
where the possible values of the akn , including n=0, are ± 1. Then Eq.(14) may be
written as:
(17)
By substituting the value of xk from Eq.(17) into Eq.(1), we obtain
(18)
(19)
where (20)
It may be seen that Q(bn) has only 2(K-1)
possible amplitude values with a sign that is given by the
instantaneous combination of bits. The computation of y is obtained by using a 2(K-1)
word
memory, a one-word initial condition register for Q(O) , and a single parallel adder sub tractor
with the necessary control-logic gates.
)1(
1
1
0 22 −−−
−
=
++−=− ∑ Nn
N
n
knkk bbx
)1(
1
1
00 22)()([
2
1 −−−
−
=
−−+−−= ∑ Nn
N
n
knknkkk bbbbx
knknkn bba −=
000 kkk bba −=
]22[
2
1 )1(
1
0
−−−
−
=
−= ∑ Nn
N
n
knk ax
]22[
2
1 )1(
1
1
0
−−−
=
−
=
−= ∑ ∑ Nn
K
k
kn
N
n
k aCY
)0(22)( )1(
1
0
QbQY Nn
N
n
n
−−−
−
=
+= ∑
∑∑ ==
==
K
k
k
K
k kn
k
n
C
andQ
a
C
bQ
11 2
)0(
2
)(
7. Computer Science & Information Technology (CS & IT) 57
4 Proposed Interpolator Design
Equiripple window based half band polyphase interpolator has been designed and implemented
using Matlab [11]. The order of the proposed interpolator is 66 with interpolation factor of 2,
transition width of 0.1 and stop band attenuation of 60 Db whose output is shown in Figure2.
Figure2. Interpolator Response
Nyquist interpolators provide same stop band attenuation and transition width with a much lower
order. In Half band filters about 50% of the coefficients of h[n] are zero. This reduces the
computational complexity of the proposed interpolator significantly.
4.1 Lth-Band Filters
Lth-band filters, of which the most popular is the half band (where L = 2), can be used to reduce
hardware complexity because many of the coefficients are zero. When a coefficient is zero, the
product of the multiplication is zero, so that particular multiplication may be omitted.
Half band filters are widely used in multirate signal processing applications when interpolating
/decimating by a factor of two. Half band filters are implemented efficiently in polyphase form,
because approximately half of its coefficients are equal to zero.
The transfer function of a half-band filter is thus given by
H(Z) = α +Z-1
E1(Z2) (21)
8. 58 Computer Science & Information Technology (CS & IT)
with its impulse response is
(22)
4.1 Design 1
The first interpolator design is has been implemented by using MAC based multiplier technique
where 67 coefficients are processed with MAC unit as shown in Figure3.
Figure3. MAC Based Multiplier Approach
4.2 Design 2
In the second interpolator design MAC unit has been replaced with LUT unit which is proposed
multiplier less technique. Here 67 coefficients are divided in two parts by using polyphase
decomposition. The proposed 2 branch polyphase interpolator structure is shown in Figure4
where interpolation takes place after polyphase decomposition to reduce the computational
complexity and can be expressed as:
H(Z) =E0 (z2
) + Z-1
E1 (z2
) (23)
=
=
,,0
,0,
]2[
otherwise
n
nh
α
9. Computer Science & Information Technology (CS & IT) 59
Figure4. Proposed Polyphase Interpolator
The coefficients corresponding to 2 branches E0(z2) and E1(z2) are processed by using
partitioned distributed arithmetic look up table technique as shown in Figure5.
Figure5. Proposed LUT based Multiplier Less Approach
Each branch is processing the required coefficients using six partitions consisting of 6 LUTs. The
two branches process the required coefficients in 6 6 6 6 6 4 and 6 6 6 6 6 3 manner respectively.
10. 60 Computer Science & Information Technology (CS & IT)
5 Hardware Simulation & Implementation
The MAC based and DA based interpolator designs have been synthesized and implemented on
Spartan-3E based 3s500efg320-4 and Virtex 2 pro target device and simulated with ISE
Simulator.
Figure6. Proposed Interpolator Response
TABLE 1 AREA & SPEED COMPARISON
Logic
Utilization
Multiplier Approach Multiplier less approach
SPARTAN 3E VIRTEX2PRO SPARTAN 3E VIRTEX2PRO
# of Slices 590 out of 4656
(12%)
594 out of
13696 (4%)
309 out of 4656 (6%) 304 out of
13696 (2%)
# of Flip Flops 643 out of 9312
(6%)
644 out of
27392 (2%)
268 out of 9312 (2%) 249 out of
27392 (0%)
# of LUTs 568 out of 9312
(6%)
567 out of
27392 (2%)
485 out of 9312 (5%) 487 out of
27392 (1%)
#of
Multipliers
1 out of 20(5%) 1 out of 136
(0%)
0 out of 20(0%) -
Speed (MHz) 52.100 82.598 61.607 92.859
11. Computer Science & Information Technology (CS & IT) 61
The ISE simulator based output response of proposed LUT based multiplierless interpolator with
16 bit input and output precision is shown in Figure6. The area and speed comparison of both
techniques has been shown in table 1. The proposed LUT based multiplier less approach has
shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with
Spartan 3E
The proposed multiplier less interpolator has consumed considerably less resources in terms of
slices, flip flops and LUTs as compared to multiplier based design.
6 Conclusions
In this paper, an optimized equiripple based half band polyphase decomposition technique is
presented to implement the proposed interpolator for wireless communication systems. The
proposed interpolator has been designed using partitioned distributed arithmetic look up table
approach to further enhance the speed and area utilization by taking optimal advantage of look up
table structure of target FPGA. The proposed LUT based multiplier less approach has shown a
a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E
The proposed multiplier less interpolator has consumed considerably less resources in terms of
slices, flip flops and LUTs and no multiplier of target device as compared to multiplier based
design to provide cost effective solution for wireless and mobile communication systems.
7 References
[1]. ShyhJye Jou, Kai-Yuan Jheng*, Hsiao-Yun Chen and An-Yeu Wu, “Multiplierless Multirate
Decimator/ Interpolator Module Generator”, IEEE Asia-Pacific Conference on Advanced System
Integrated Circuits, pp. 58-61, Aug-2004.
[2]. Vijay Sundararajan, Keshab K. Parhi, “Synthesis of Minimum-Area Folded Architectures for
Rectangular Multidimensional”, IEEE TRANSACTIONS ON SIGNAL PROCESSING, pp. 1954-
1965, VOL. 51, NO. 7, JULY 2003.
[3] S K Mitra, Digital Signal Processing, Tata Mc Graw Hill, Third Edition, 2006.
[4] Ali AI-Haj, “An Efficient Configurable Hardware Implementation of Fundamental Multirate
Filter Banks”, 5th International Multi-Conference on Systems, Signals and Devices, pp.1-5, IEEE
SSD 2008.
[5] Binming Luo, Yuanfu Zhao, and Zongmin Wang, “An Area-efficient Interpolator Applied in
Audio Σ-DAC” Third International IEEE Conference on Signal-ImageTechnologies and Internet-
Based System, pp.538-541, 2008.
[6] N.M.Zawawi, M.F.Ain, S.I.S.Hassan, M.A.Zakariya, C.Y.Hui and R.Hussin, “Implementing
WCDMA Digital Up Converter In FPGA” IEEE INTERNATIONALRF AND MICROWAVE
CONFERENCE, pp. 91-95, RFM-2008.
[7] Patrick Longa and Ali Miri “Area-Efficient FIR Filter Design on FPGAs using Distributed
Arithmetic”, pp248-252 IEEE International Symposium on Signal Processing and Information
Technology,2006.
12. 62 Computer Science & Information Technology (CS & IT)
[8] Pramod Kumar Meher, , Shrutisagar Chandrasekaran, , and Abbes Amira,” FPGA Realization of
FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic” IEEE
TRANSACTIONS ON SIGNAL PROCESSING, VOL. 56, NO. 7, JULY 2008
[9] M. Yamada, and A. Nishihara, “High-Speed FIR Digital Filter with CSD Coefficients
Implemented on FPGA”, in Proc. IEEE Design Automation Conference (ASP-DAC 2001), 2001,
pp. 7-8.
[10]. D.J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. Anderson, “A Novel High Performance
Distributed Arithmetic Adaptive Filter Implementation on an FPGA”, in Proc. IEEE Int.
Conference on Acoustics, Speech, and Signal Processing(ICASSP’04), Vol. 5, pp. 161-164, 2004
[11]. Mathworks, “Users Guide Filter Design Toolbox 4”, March-2007.
Authors
Rajesh Mehra: Mr. Rajesh Mehra is currently Assistant Professor at National Institute of
Technical Teachers’ Training & Research, Chandigarh, India. He is pursuing his PhD from Panjab University,
Chandigarh, India. He has completed his M.E. from NITTTR, Chandigarh, India and B.Tech. from NIT,
Jalandhar, India. Mr. Mehra has 14 years of academic experience. He has authored more than 30
research papers in national, international conferences and reputed journals. Mr. Mehra’s interest areas
are VLSI Design, Embedded System Design, Advanced Digital Signal Processing, Wireless & Mobile
Communication and Digital System Design. Mr. Mehra is life member of ISTE
Ravinder Kaur is currently Senior Lecturer at Govt. polytechnic college,Punjab.She is
pursuing her ME from NITTTR, Chandigarh, India and had done B.E from NIT, Srinagar, India.Ms Kaur has
23years professional experience. Ms Kaur interest areas are, Multirate Digital Signal Processing, Wireless
& Mobile Communication and FPGA based embedded System Design