Unit1_Part2-Machine_Instructions_Programs_7_9_2018_3pm.ppt

Unit-1
Basic Structure of Computers: Computer Types, Functional Units, Basic
Operational Concepts, Bus Structures, Performance - Processor Clock, Basic
Performance Equation, Pipelining and Superscalar, Clock Rate, Instruction
set: CISC &RISC, Compiler, Performance Measurement, Historical
Perspective.
Machine Instructions and Programs: Numbers, Arithmetic Operations
and Characters, Memory Location and Addresses, Memory Operations,
Instructions and Instruction Sequencing, Addressing Modes, Assembly
Language, Basic Input and Output Operations, Stacks and Queues,
Subroutines, Additional Instructions, Encoding of Machine Instructions.
3 September 2022 CSE, BMSCE 1

Topics Covered in Todays Class
Unit 1: Machine Instructions and Programs: Numbers,
Arithmetic Operations and Characters, Memory Location and
Addresses, Memory Operations, Instructions and Instruction
Sequencing, Addressing Modes, Assembly Language, Basic Input
and Output Operations, Stacks and Queues, Subroutines,
Additional Instructions, Encoding of Machine Instructions.

Numbers, Arithmetic Operations and
Characters

Three major representations of Signed Integer
1. Sign and magnitude
2. One’s complement
3. Two’s complement

Decimal Number Representation or Base 10
In Decimal or Base 10 System, digits used are:
0 1 2 3 4 5 6 7 8 9
Representing 537 (Five hindered and thirty
Seven)

Binary Number Representation or Base 2
 Binary Digit or Bit is the smallest unit of
computation on most digital computers
 Bit has two states
 0 represents zero voltage (0v) or ground
 1 represents positive voltage (+5v)

Power of 2 Calculation Value
20 1 1
21 2 2

Decimal Binary
0 00
1 01
2 10
3 11
20 1 1
21 2 2

Decimal Binary
0 00 21 * 0 + 20 * 0 = 2*0 +1*0 = 0+0=0
1 01
2 10
3 11
20 1 1
21 2 2

Decimal Binary
0 00 21 * 0 + 20 * 0 = 2*0 +1*0 = 0+0=0
1 01 21 * 0 + 20 * 1 = 2*0 +1*1 =0+1= 1
2 10 21 * 1 + 20 * 0 = 2*1 +1*0 = 2+0=2
3 11 21 * 1 + 20 * 1 = 2*1 +1*1 = 2+1=3
20 1 1
21 2 2

Example: 3-bit binary numbers
Decimal Binary
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
20 1
21 2 2
22 2 * 2 4

Question: List out all 4-bit binary numbers
Decimal Binary
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
20 1
21 2 2
22 2 * 2 4
23 2 * 2 * 2 8

Example: 4-bit binary numbers
Decimal Binary
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111
20 1
21 2 2
22 2 * 2 4
23 2 * 2 * 2 8

Representation of a Binary Number
 Converting from decimal to binary (base 10 to base 2) will also
produce a weighted binary number with the right-hand most
bit being the Least Significant Bit or LSB, and the left-hand
most bit being the Most Significant Bitor MSB, and we can
represent this as:
 Convert binary to decimal by finding the decimal equivalent of
the binary array of digits 1011001012 and expanding the
binary digits into a series with a base of 2giving an equivalent
of 35710 in decimal or denary.
(256) + (64) + (32) + (4) + (1) = 35710

Question: Convert the following Binary number to Decimal
 Binary number: 100011

Answer
 Binary number: 100011
 Equivalent Decimal number is: 35

Decimal to Binary Conversion

Question: Represent the following Decimal number in 7-bit
binary numbers
Decimal
7-bit Binary
Number
5
14
26
53

Answer
Decimal
7-bit Binary
Number
5 0000101
14 0001110
26 0011010
53 0110101

Question
 What is the biggest decimal number
that you can represent in binary using
8-bit ?
 How many different decimal number
8-bit ?

Answer
What is the biggest decimal number
8-bit ?
 255 (i.e., 28 -1=256-1=255)
How many different decimal number
8-bit ?
 0 to 255 i.e., 256 decimal numbers

Signed Binary Number Representation
 We can use a single bit to identify the sign of a signed binary number as being positive or
negative in value. So to represent a positive binary number (+n) and a negative (-n) binary
number, we can use them with the addition of a sign.
 For signed binary numbers the most significant bit (MSB) is used as the sign bit. If the sign bit
is “0”, this means the number is positive in value. If the sign bit is “1”, then the number is
negative in value. The remaining bits in the number are used to represent the magnitude of
the binary number in the usual unsigned binary number format way.
 Then we can see that the Sign-and-Magnitude (SM) notation stores positive and negative
values by dividing the “n” total bits into two parts: 1 bit for the sign and n–1 bits for the value
which is a pure binary number. For example, the decimal number 53 can be expressed as an
8-bit signed binary number as follows:

Example: Signed numbers

1’s (One’s) complement number representation
 If all bits in a byte are inverted by changing each 1 to 0
and each 0 to 1, we have formed the one’s complement
of the number.

Binary Sign-Magnitude and One’s Complement
representation

Two’s Complement
The two’s complement is a method for representing positive and negative
integer values in binary. The useful part of two’s complement is that it
automatically includes the sign bit.
Rule: To form the two’s complement, add 1 to the one’s complement.
Step 1: Begin with the original binary value
10011001 Original binary number
Step 2: Find the one's complement
01100110 One's complement
Step 3: Add 1 to the one's complement
01100110 One's complement
+ 1 Add 1
-----------
01100111 <--- Two's complement

Two’s Complement
The two’s complement is a method for representing positive and negative
integer values in binary. The useful part of two’s complement is that it
automatically includes the sign bit.
Rule: To form the two’s complement, add 1 to the one’s complement.

Binary Sign-Magnitude, One’s Complement representation
and Two’s Complement

Conversion of Negative Numbers to Two’s Complement
 These examples show conversion of a decimal number to 4-bit twos
complement.
 The bit size is always important with twos complement, since you
must be able to tell where the sign bit is.
 The steps are simple.
 First, you convert the magnitude of the number to binary, and pad to the
word size (4 bits).
 If the original number was positive, you are done.
 Otherwise, you must negate the binary number by inverting the bits and
adding 1.

complement.
 The bit size is always important with twos complement, since you must
be able to tell where the sign bit is.
word size (4 bits).
adding 1.
 Convert -6 to an 4-bit, twos complement binary number.
 Convert the magnitude, 6 to binary. So 610 = 1102.
 Pad to 8 bits: 0110
 Negate the number by inverting the bits and adding 1.
0110
Negate 1001
Add 1 1
--------
1010 Two’s complement of -6

complement.
 The bit size is always important with twos complement, since you must
be able to tell where the sign bit is.
word size (8 bits).
adding 1.
 Convert the magnitude, 72 to binary. So 7210 = 10010002.
 Pad to 8 bits: 01001000

Question
 Using 7 bits to represent each number, write the
representations of 23 and -23 in signed magnitude and
2's complement integers

Answer
 Using 7 bits to represent each number, write the
representations of 23 and -23 in signed magnitude and
2's complement integers

Question
Represent the decimal values 5, -2, 14, -10, 26, -19, 51 and
-43 as signed 7-bit numbers in the following formats
a. Sign-Magnitude
b. 1’s complement
c. 2’s complement

Answer
Represent the decimal values 5, -2, 14, -10, 26, -19, 51 and
-43 as signed 7-bit numbers in the following formats
a. Sign-Magnitude
b. 1’s complement
c. 2’s complement

word size (8 bits).
adding 1.
 Convert the magnitude, 72 to binary. So 7210 = 10010002. 01001001
 Pad to 8 bits: 01001000
 So, -7210 is 10111000 as an eight-bit, two's complement number.

 Convert 47 to an 8-bit, twos complement binary number. This is
positive, so all that is needed is to convert to binary and pad to eight
bits. So 4710 = 1011112. So 47 as an 8-bit two's complement number
is just 00101111.
 Convert -109 to an 8-bit, twos complement number. So 10910 =
11011012.
 Convert -67 to an 8-bit, twos complement number. So 6710 = 10000112.
 Convert 81 to an 8-bit, twos complement number. Since this is positive, it's just
a matter of converting to binary and padding to 8 bits. So 8110 = 10100012,
giving 01010001

4-bit Signed Binary Number Comparison
Decimal Signed Magnitude Signed One’s Complement Signed Two’s Complement
+7 0111 0111 0111
+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
+0 0000 0000 0000
-0 1000 1111 –
-1 1001 1110 1111
-2 1010 1101 1110
-3 1011 1100 1101
-4 1100 1011 1100
-5 1101 1010 1011
-6 1110 1001 1010
-7 1111 1000 1001

Under Signed Number Representation
 Number of bits used for
representation is important because
Under 8-bit representation
00000101 +5
10000101 -5
Under 4-bit representation
0101 +5
1101 -5

Problem with arithmetic
 Under Sign-magnitude representation
 Under One’s Complement representation
Sign-Magnitude (4-bit Representation)
Adding
+5-5
0101 +5
1101 -5
Total 10010
(1
Carryout)
INCORRECT, because he result
should be zero i.e., 00000
One’s Complement (4-bit Representation)
Adding
+5-5
0101 +5
1010 -5
One’s Complement of -5
Total 1111 INCORRECT, because the result
should be zero i.e., 00000
But it is Minus Zero

Arithmetic under Two’s Complement
Decimal Signed Two’s Complement
+7 0111
+6 0110
+5 0101
+4 0100
+3 0011
+2 0010
+1 0001
+0 0000
-0 –
-1 1111
-2 1110
-3 1101
-4 1100
-5 1011
-6 1010
-7 1001
Two’s Complement
(4-bit Representation)
Adding
+5-5
0101 +5
1011 -5
Total 10000
(1
Carryout)
CORRECT(Zero)
Ignore the
Carryout
Two’s Complement
(4-bit Representation)
Adding
+6-2
0110 +6
1110 -2
Total 10100
(1
Carryout)
CORRECT(+4)
Ignore the
Carryout

Subtraction by 2’s Complement
The operation is carried out by means of the
following steps:
(i) At first, 2’s complement of the subtrahend is
found.
(ii) Then it is added to the minuend.
(iii) If the final carry over of the sum is 1, it is
dropped and the result is positive.
(iv) If there is no carry over, the two’s
complement of the sum will be the result and it is
negative

Example of Two’s Complement Subtraction
 Example of Subtracting 13 from 19

Test Your knowledge
Convert the following pairs of decimal
numbers to 5-bit 2’s-complement
numbers, then add them.
a. -5 and 7 b. -3 and -8

Example of two’s Complement Arithmetic

Arithmetic Overflow
 In 2's complement number representation system, n bits
can represent values in the range (-2n-1) to (+2n-1 – 1).
 When the result of an arithmetic operation is outside the
representable range, an arithmetic overflow has
occurred.

Arithmetic Overflow
Care must be taken when adding numbers of like sign
since overflow can occur.
 If you add two numbers of like sign and the result is of the opposite
sign, then the result cannot be used. This "overflow" condition occurs
because, in order to represent the result, we would need more bits
than are available in the bit field. (Remember, we can't just "enlarge"
the size of the result- it must remain the same size as the operands.)
Here are examples for adding two negative numbers, and adding two
positive numbers, each of which results in overflow.

Test Your Knowledge
Convert the following pairs of decimal numbers to 5-bit 2’s-
complement numbers, then add them. State whether or not
overflow occurs in each case
a. 7 and 13 b. -10 and -13

Question
Convert the following pairs of decimal numbers to 5-bit 2’s-
complement numbers, then add them. State whether or not
overflow occurs in each case
a. 5 and 10
b. 7 and 13
c. -14 and 11
d. -5 and 7
e. -3 and -8
f. -10 and -13

Question
Repeat for subtraction operation, where the second number
of each pair to be subtracted from first number. State
whether or not overflow occurs in each case
a. 5 and 10
b. 7 and 13
c. -14 and 11
d. -5 and 7
e. -3 and -8
f. -10 and -13

How to avoid Overflow
 You can enlarge the size of the bit field, but only before you perform any
operations, and it must be done a certain way. If you find that the size of
the bit field is too small and overflow is occurring, you can promote the values to
larger bit fields. This is done by a technique called sign extension. To enlarge the
bit field, add bits on the left, duplicating the most significant bit. This preserves
the sign of the number and does not alter its value. Remember, you must
promote all values to the same size. The table below illustrates sign-extension of
a 4-bit number to 5, 6, and 8-bit fields. In each case, the most significant bit of
the original 4-bit field (in blue) is simply repeated as many times as necessary on
the left(in red).

Unit1:Memory Locations and Addresses

Memory Locations and Addresses

second word
first word
nbits
last word
i th word
•
•
•
•
•
•
Address
0
1
M-1

3 September 2022 CSE, BMSCE
Address
Length
K-bits
Addressable
Locations
2k
2 22=4 Locations
3 23=8 Locations
4 24=16 Locations
Address
K=2bits
Word Length
n =8bits = 1 Byte
0 00 0000 0110
1 01 0000 0111
2 10 0000 1000
3 11 0000 1010
1st Byte or word
2nd Byte or word
4th Byte or word
3rd Byte or word
Memory

Address
Length
K-bits
Addressable
Locations
2k
2 22=4 Locations
3 23=8 Locations
4 24=16 Locations
Address
K=3bits
Word Length
n =8bits = 1 Byte
0 000 0000 0110
1 001 0000 0111
2 010 0000 1000
3 011 0000 1010
4 100 0000 1011
5 101 0000 1100
6 110 0000 1101
7 111 0000 1110
1st Byte or word
2nd Byte or word
4th Byte or word
3rd Byte or word
5th Byte or word
6th Byte or word
7th Byte or word
8th Byte or word
Memory

Question
Address
Length
K-bits
Addressable
Locations
2k
2 22=4 Locations
3 23=8 Locations
4 24=16 Locations
Address
K=3bits
Word Length
n =8bits = 1 Byte
0 000 0000 0110
1 001 0000 0111
2 010 0000 1000
3 011 0000 1010
4 100 0000 1011
5 101 0000 1100
6 110 0000 1101
7 111 0000 1110
1st Byte or word
2nd Byte or word
4th Byte or word
3rd Byte or word
5th Byte or word
6th Byte or word
7th Byte or word
8th Byte or word
Question:
Consider in one memory location,
One byte of information can be stored
i.e., n=8bits. To store 1024 bytes of information
How many address bits should be used
i.e., what should be the k value ?
Memory

Question
Address
Length
K-bits
Addressable
Locations
2k
2 22=4 Locations
3 23=8 Locations
4 24=16 Locations
Address
K=3bits
Word Length
n =8bits = 1 Byte
0 000 0000 0110
1 001 0000 0111
2 010 0000 1000
3 011 0000 1010
4 100 0000 1011
5 101 0000 1100
6 110 0000 1101
7 111 0000 1110
1st Byte or word
2nd Byte or word
4th Byte or word
3rd Byte or word
5th Byte or word
6th Byte or word
7th Byte or word
8th Byte or word
Question:
Consider in one memory location,
One byte of information can be stored
i.e., n=8bits. To store 1024 bytes of information
How many address bits should be used
i.e., what should be the k value ? Kilo Bytes
(103) or
1024
Bytes
210 =1024
Therefore number of address
bits should be 10 bits
Answer

Two ways of Byte address assignment across words
 Big-endian and little-endian are terms that
describe the order in which a sequence
of bytes are stored in computer memory.
 Big-endian is an order in which the "big end"
(most significant value in the sequence) is
stored first (at the lowest storage address).
 Little-endian is an order in which the "little
end" (least significant value in the sequence) is
stored first.

 Example: Consider storing the number 2064 i.e., Two thousand
Sixty four. We will assume one digit occupies 4bits.
2064 2 0 6 4
0010 0000 0110 0100
MSB
Most Significant
Byte
LSB
Least Significant
Byte

 Example: Consider storing the number 2064 i.e., Two thousand
Sixty four. We will assume one digit occupies 4bits.
2064 2 0 6 4
0010 0000 0110 0100
MSB
Most Significant
Byte
LSB
Least Significant
Byte
Address
Word Length
n=8bits=1 Byte
00 0010 0000 20 MSB
01 0110 0100 64 LSB
Address
Word Length
n=8bits=1 Byte
00 0110 0100 64 LSB
01 0010 0000 20 MSB
Big-Endian Approach Little-Endian Approach

Big-Endian and Little-Endian Assignments
 Big-Endian: lower byte addresses are used for the most significant bytes of the
word
 Little-Endian: opposite ordering. lower byte addresses are used for the less
significant bytes of the word
2
k
4
- 2
k
3
- 2
k
2
- 2
k
1
- 2
k
4
-
2
k
4
-
0 1 2 3
4 5 6 7
0
0
4
2
k
1
- 2
k
2
- 2
k
3
- 2
k
4
-
3 2 1 0
7 6 5 4
Byte address
Byte address
(a) Big-endian assignment (b) Little-endian assignment
4
Word
address
•
•
•
•
•
•
Figure :. Byte and word addressing.

Hexadecimal numbers
 A group of 4 bits can take any value between 0 (0000 binary) and 15 (1111 binary).
 In hexadecimal, we replace each group of 4 bits with a single digit to represent the value 0 to
15. Since we only have digits 0 to 9, we use letters A to E to represent values 10 to 15. Here is
a table of binary, denary and hex values:
Note: To specify
Hexadecimal numbers
Prefix 0x will be used
i.e.,
0x123
or
123h

Question
 Consider a computer has a byte-addressable memory organized in 32-
bit words according to the big-endian scheme. A program reads ASCII
characters entered at a keyboard and stores them in successive byte
locations, starting at location 1000. Show the contents of the two
memory words at locations 1000 and 1004 after the word “computer”
has been entered. Values corresponding to the characters are as
shown below:
Hex
c 0x63
o 0x6F
m 0x6D
p 0x70
u 0x75
t 0x74
e 0x65
r 0x72

Answer
 Consider a computer has a byte-addressable memory organized in 32-bit words
according to the big-endian scheme. A program reads ASCII characters entered
at a keyboard and stores them in successive byte locations, starting at location
1000. Show the contents of the two memory words at locations 1000 and 1004
after the word “computer” has been entered. Values corresponding to the
characters are as shown below:
Address
Word Length
n=8bits=1 Byte
1000 0110 0011 c 63 MSB
1001 0110 1111 o 6F
1002 0110 1101 m 6D
1003 0111 0000 p 70
1004 0111 0101 u 75
1005 0111 0100 t 74
1006 0110 0101 e 65
1007 0111 0010 r 72 LSB
Big-Endian Approac
Hex
c 63
o 6F
m 6D
p 70
u 75
t 74
e 65
r 72

Question
according to the Little-endian scheme. A program reads ASCII characters
entered at a keyboard and stores them in successive byte locations, starting at
location 1000. Show the contents of the two memory words at locations 1000
and 1004 after the word “computer” has been entered. Values corresponding to
the characters are as shown below:
Hex
c 63
o 6F
m 6D
p 70
u 75
t 74
e 65
r 72

Answer
according to the Little-endian scheme. A program reads ASCII characters
entered at a keyboard and stores them in successive byte locations, starting at
location 1000. Show the contents of the two memory words at locations 1000
and 1004 after the word “computer” has been entered. Values corresponding to
the characters are as shown below:
Address
Word Length
n=8bits=1 Byte
1000 0110 0011 r 72 LSB
1001 0110 1111 e 65
1002 0110 1101 t 74
1003 0111 0000 u 75
1004 0111 0101 p 70
1005 0111 0100 m 6D
1006 0110 0101 o 6F
1007 0111 0010 c 63 MSB
Little-Endian
Approach
Hex
c 63
o 6F
m 6D
p 70
u 75
t 74
e 65
r 72
1000: 72 65 74 75
r e t u
1004: 70 6D 6F 63
p m o c

Memory Word Alignment
 Words are said to be Aligned in memory if they
begin at a byte-address that is a multiple of
number of bytes in a word.
 For example,
 If the word length is 16 (2 Bytes), aligned words
begin at byte addresses 0, 2, 4,....
 If the word length is 32 (4 Bytes), aligned words
begin at byte addresses 0, 4, 8,....
 Words are said to have Unaligned Addresses, if
they begin at an arbitrary byte-address

Memory Operations

INSTRUCTIONS and INSTRUCTION SEQUENCING

Instructions
A computer must have instruction capable of
performing the following operations. They are:
 Data transfer between memory and processor
register (Ex.: MOV, LOAD, STOREPUSH, POP )
 Arithmetic and logical operations on data (Ex.:
ABB, SUB, DIV, MUL)
 Program sequencing and control (Ex.: LOOP,
CALL,RET)
 I/O transfer (Ex. IN, OUT).

Register Transfer Notation
The possible locations that may be involved during data
transfer are
1. Memory Location
2. Processor register
3. Registers in I/O sub-system.

Assembly Language Notation:
 To represent machine instructions and
programs, assembly language format is used

Instruction Set Categories
Instruction Set Categories based on the Operands
explicitly specified in the instruction
1. Three-address or 3-Operand instructions
2. Two-address or 2-Operand instructions
3. One-address or 1-Operand instructions
4. Zero-address or 0-Operand instructions

Three-address or 3-Operand instructions
 Three Operands will be specified in the instructions
 General Format:
 Example: ADD A, B, C
 C <- [A]+[B] Meaning: Add the contents of the memory location A and B ; And
Store the result in memory location C
Operation Source
Operand1
Source
Operand2
Destination
Operand

Three-address or 3-Operand instructions
 Three Operands will be specified in the instructions
 General Format:
 Example: ADD A, B, C
 C <- [A]+[B] Meaning: Add the contents of the memory location A and B ; And
Store the result in memory location C
Operation Source
Operand1
Source
Operand2
Destination
Operand
ADD A, B, C
Before Executing the Instruction After Executing the Instruction
Addr Memory
Contents
A 0x1000 8
B 0x1001 2
C 0x1002 5
Addr Memory
Contents
A 0x1000 8
B 0x1001 2
C 0x1002 10

Question
Write a program to evaluate the arithmetic expression
RESULT=A*B + C*D
Using a general register computer with three-operand instructions. Assume
the processor has MULTIPLY and ADD instructions. Do not modify the
values of A, B, C, D. Use the temporary memory locations TEMP1 and
TEMP2 to store the intermediate results if necessary.
Assume the instruction format of the form:
OPCODE SourceOperand1, SourceOperand2, DestinationOperand
Note: So, a 3- Operand machine has instructions like ADD X, Y, Z. This
instruction will perform Z ← [X] + [Y]. In words, this takes the content of
the memory location specified by the address X, adds it to the content of
the memory location specified by the address Y, and places the result in the
memory location specified by the address Z.

Question
RESULT=A*B + C*D
Using a general register computer with three-operand instructions. Assume
the processor has MULTIPLY and ADD instructions. Do not modify the
values of A, B, C, D. Use the temporary memory locations TEMP1 and
TEMP2 to store the intermediate results if necessary.
OPCODE SourceOperand1, SourceOperand2, DestinationOperand
Note: So, a 3- Operand machine has instructions like ADD X, Y, Z. This
instruction will perform Z ← [X] + [Y]. In words, this takes the content of
the memory location specified by the address X, adds it to the content of
the memory location specified by the address Y, and places the result in the
memory location specified by the address Z.
ANSWER
MULTIPLY A, B, TEMP1
MULTIPLY C, D, TEMP2
ADD TEMP1, TEMP2, RESULT

Two-address or 2-Operand instructions
 Two Operands will be specified in the instructions
 General Format:
 Example: ADD A, B
 B <- [A]+[B] Meaning : Add the contents of the memory location A and B ; And
Store the result in memory location B
Operation Source
Operand
Destination
Operand

 Two Operands will be specified in the instructions
 General Format:
 Example: ADD A, B
 B <- [A]+[B] Meaning : Add the contents of the memory location A and B ; And
Store the result in memory location B
Operation Source
Operand
Destination
Operand
ADD A, B
Addr Memory
Contents
A 0x1000 8
B 0x1001 2
C 0x1002 5
Addr Memory
Contents
A 0x1000 8
B 0x1001 10
C 0x1002 5

Using Two-address instructions, write complete set of
instructions to perform
 C=A+B
i.e., C <- [A]+[B] Meaning: Add the contents of the memory location A and
B ; And Store the result in memory location C
ANSWER
We will use MOVE instruction
MOVE B, C //C <- [B] Move the contents of memory location B to Memory
//Location C
ADD A, C //Add the contents of Memory location A with C. And store the result
//in the memory location C

Question
RESULT=A*B + C*D
Using a general register computer with two-operand instructions. Assume the
processor has MULTIPLY and ADD instructions. Do not modify the values of A, B, C,
D. Use the temporary memory locations TEMP1 and TEMP2 to store the intermediate
results if necessary.
OPCODE SourceOperand, DestinationOperand
Note: So, a 2- Operand machine has instructions like ADD X, Y. This instruction will
perform Y ← [X] + [Y]. In words, this takes the content of the memory location
specified by the address X, adds it to the content of the memory location specified by
the address Y, and places the result in the memory location specified by the address Y.
Similarly we have MOVE instruction of the format MOVE SourceOperand,
DestinationOperand

Answer
RESULT=A*B + C*D
Using a general register computer with two-operand instructions. Assume the
processor has MULTIPLY and ADD instructions. Do not modify the values of A, B, C,
D. Use the temporary memory locations TEMP1 and TEMP2 to store the intermediate
results if necessary.
OPCODE SourceOperand, DestinationOperand
Note: So, a 2- Operand machine has instructions like ADD X, Y. This instruction will
perform Y ← [X] + [Y]. In words, this takes the content of the memory location
specified by the address X, adds it to the content of the memory location specified by
the address Y, and places the result in the memory location specified by the address Y.
Similarly we have MOVE instruction of the format MOVE SourceOperand,
DestinationOperand
ANSWER
MOVE A, TEMP1
ADD B, TEMP1
MOVE C, TEMP2
ADD D, TEMP2
MOVE TEMP2, RESULT

Homework Problem
Write a program to evaluate the arithmetic statement:
1. Using a general register computer with three-operand
instructions
2. Using a general register computer with two-operand instructions
computer with zero address instructions (stack instructions)
Do not modify the values of A, B, C, D, E, F or G. Use a temporary
location T to store the intermediate results if necessary.

One-address or 1-Operand instructions
 Only one Operand will be specified in the instructions.
 Accumulator Register will be used as second Operand
 General Format:
 Example: ADD A
 Acc <- [Acc]+[A] Meaning : Add the contents of accumulator with the memory
location A ; And Store the result in the accumulator register
Operation Source/Destination Operand

One-address or 1-Operand instructions
 Only one Operand will be specified in the instructions.
 Accumulator Register will be used as second Operand
 General Format:
 Example: ADD A
 Acc <- [Acc]+[A] Meaning : Add the contents of accumulator with the memory
location A ; And Store the result in the accumulator register
Operation Source/Destination Operand
ADD A
Addr Memory
Contents
A 0x1000 8
Accumulator Register 2
Addr Memory
Contents
A 0x1000 8
Accumulator Register 10

Question
RESULT=A*B + C*D
in a single accumulator processor. Assume the processor has load,
store, multiply and add instructions and that all values fit in the
accumulator. Do not modify the values of A, B, C, D, E, F or G.
Use a temporary location RESULT to store the intermediate results
if necessary.
Note:
Load A ;will load accumulator with the contents of the memory location A
Store A ;will store the contents of the accumulator into memory location A
Add A ;will add contents of accumulator with memory location A and
; store the result into accumulator

Answer
RESULT=A*B + C*D
in a single accumulator processor. Assume the processor has load,
store, multiply and add instructions and that all values fit in the
accumulator. Do not modify the values of A, B, C, D, E, F or G.
Use a temporary location RESULT to store the intermediate results
if necessary.

Zero-address or 0-Operand instructions
 Locations of the operands are defined implicitly.
 Stack will be used to store operands
 General Format:
 Example: ADD Top two elements of the stack will popped and sum of the
popped numbers will pushed on to stack
Operation

 Locations of the operands are defined implicitly.
 Stack will be used to store operands
 General Format:
 Example: ADD Top two elements of the stack will popped and sum of the
popped numbers will pushed on to stack
Operation
ADD
8
2
Stack
TOS
TOS: Top of the Stack
8
2 10
Stack
TOS

Using Zero-address instructions, write complete set of instructions to
perform C=A+B

perform C=A+B
Before Executing the Instructions After Executing the Instructions
Stack
TOS
Addr Memory Contents
A 0x1000 8
B 0x1001 2
C 0x1002 4
ANSWER
PUSH A
PUSH B
ADD
POP C

perform C=A+B
Before Executing the Instructions After Executing the Instructions
Stack
TOS
A 0x1000 8
B 0x1001 2
C 0x1002 4
2
8 10
Stack
TOS
A 0x1000 8
B 0x1001 2
C 0x1002 10
ANSWER
PUSH A
PUSH B
ADD
POP C

Question
X=(A+B) * (C+D)
Using a stack organized computer with zero address instructions (stack
instructions)

Answer
X=(A+B) * (C+D)
Using a stack organized computer with zero address instructions (stack
instructions)

Question
Write set of instructions to implement the expression
A = (B – C)*D
on 3, 2, 1, and 0-address machines.
Do not rearrange the expression.
Do not modify the values of B, C and D
Note:
Assume that you have addition (ADD), subtraction (SUB), multiplication (MPY), and
data movement (MOV, LOAD, STORE, PUSH, and POP) instructions available to you in
each of the relevant types of machines. Recall that an n-address machine will specify n
operand addresses in the instruction. So, a 3-address machine has instructions like
ADD X, Y, Z. This instruction will perform M[X] ← M[Y] + M[Z]. In words, this takes
the content of the memory location specified by the address Y, adds it to the content
of the memory location specified by the address Z, and places the result in the
memory location specified by the address X. Also, keep in mind that 1-address
machines use an accumulator to hold one source operand or the destination operand,
and 0- address machines use a stack to store both source operands and destination
operands. Finally, you may assume that a memory location can be both a source and a
destination. Note that in all cases in this solution that we read instructions such that
SUB A, B, C will perform A = B – C. Similarly, SUB A, B will perform A = A – B.

Answer
Write set of instructions to implement the expression A = (B – C)*D
on 3, 2, 1, and 0-address machines. Do not rearrange the expression.
Assume that you have addition (ADD), subtraction (SUB), multiplication (MPY), and
data movement (MOV, LOAD, STORE, PUSH, and POP) instructions available to you in
each of the relevant types of machines. Recall that an n-address machine will specify n
operand addresses in the instruction. So, a 3-address machine has instructions like
ADD X, Y, Z. This instruction will perform M[X] ← M[Y] + M[Z]. In words, this takes
the content of the memory location specified by the address Y, adds it to the content
of the memory location specified by the address Z, and places the result in the
memory location specified by the address X. Also, keep in mind that 1-address
machines use an accumulator to hold one source operand or the destination operand,
and 0- address machines use a stack to store both source operands and destination
operands. Finally, you may assume that a memory location can be both a source and a
destination. Note that in all cases in this solution that we read instructions such that
SUB A, B, C will perform A = B – C. Similarly, SUB A, B will perform A = A – B.
Answer:
The table below shows the four programs that are needed to answer this question.

Question
 In case of, Zero-address instruction method the
operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack

Answer
 In case of, Zero-address instruction method the
operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack

Question
 In case of, One-address instruction method, one of the
operand is implicitly stored in _____
a) General Purpose Registers
b) Accumulator
c) Push down stack

Answer
 In case of, One-address instruction method, one of the
operand is implicitly stored in _____
a) General Purpose Registers
b) Accumulator
c) Push down stack

Homework Problem
Write a program to evaluate the arithmetic statement:
1. Using a general register computer with three-operand
instructions
2. Using a general register computer with two-operand instructions
3. Using an accumulator type computer with one-operand
instructions
4. Using a stack organized computer with zero address instructions
(stack instructions)
Do not modify the values of A, B, C, D, E, F or G. Use a temporary
locations to store the intermediate results if necessary.

Answer
3-address 2-address 1-address 0-address
MULT D, D, E
SUB D, D, F
MULT C, C, D
SUB A, A, B
ADD A, A, C
MULT H, H, K
ADD G, G, H
DIV X, A, G
MULT D, E
SUB D, F
MULT C, D
SUB A, B
ADD A, C
MULT H, K
ADD G, H
DIV A, G
STA X, A
PUSH H
MULT K
ADD G
POP G
PUSH D
MULT E
SUB F
MULT C
ADD B
POP B
PUSH A
SUB B
POP A
DIV G
POP X
PUSH D
PUSH E
MULT
PUSH F
SUB
PUSH C
MULT
PUSH B
ADD
POP B
PUSH A
PUSH B
SUB
POP A
PUSH H
PUSH K
MULT
PUSH G
ADD
POP G
PUSH A
PUSH G
DIV
POP X

Instruction Types based on number of operands in the instruction

Addressing Modes

Addressing Modes
The term addressing modes refers to the way in which the
operand of an instruction is specified. Information contained
in the instruction code is the value of the operand or the
address of the operand. Following are the main addressing
modes that are used on various platforms and architectures.
1. Register Addressing Mode
2. Immediate Addressing Mode
3. Direct (or Absolute) Addressing Mode
4. Indirect Addressing Mode
5. Index Addressing Mode
6. Relative Addressing Mode
7. Auto increment Addressing Mode
8. Auto decrement Addressing Mode

Register Addressing Mode
 The operand is the content of a processor register.
Register name is specified in the instruction.
 Effective Address of the Operand: Register name
specified in the instruction
ADD R0, R1 ; R1 <- R0 + R1
Registers Contents
R0 8
R1 2
Registers Contents
R0 8
R1 10

Register Addressing Mode
 The operand is the content of a processor register.
Register name is specified in the instruction.
 Effective Address of the Operand: Register name
specified in the instruction
Move R0, R1 ; R1 <- R0
Registers Contents
R0 8
R1 2
Registers Contents
R0 8
R1 8

Immediate Addressing Mode
 The operand is given explicitly in the instruction
 Effective Address of the Operand: Operand value given in the
instruction
ADD #10, R1 ; R1 <- 10 + R1
Registers Contents
R1 2
Registers Contents
R1 12

Immediate Addressing Mode
 The operand is given explicitly in the instruction
 Effective Address of the Operand: Operand value given in the
instruction
Move #10, R1 ; R1 <- 10
Registers Contents
R1 2
Registers Contents
R1 10

Direct(or Absolute) Addressing Mode
 The operand is a Memory location. The address of the
memory location is given in the instruction explicitly.
 Effective Address of the Operand: Address of the
memory location given directly in the instruction
ADD LOCA, R1
Addr Memory
Contents
LOCA 0x1000 8
R1 2
Addr Memory
Contents
LOCA 0x1000 8
R1 10

Indirect Addressing Mode
 Here neither the operands nor the their addresses are given explicitly.
The instruction provides the information from which the address of the
operand is determined i.e., the instruction provides effective address of
the operand using register or memory location. The indirection is
denoted by () sign around register or memory.
 Effective Address of the Operand: (Ri) or (LOCA) is the contents of a
register or the memory location whose address appears in the
instruction
ADD (LOCA), R1
Addr Memory
Contents
LOCA 0x1000 0x2000
0x2000 8
R1 2
Addr Memory
Contents
LOCA 0x1000 0x2000
0x2000 8
R1 10

Indirect Addressing Mode
 Here neither the operands nor the their addresses are given explicitly. The
instruction provides the information from which the address of the operand is
determined i.e., the instruction provides effective address of the operand using
register or memory location. The indirection is denoted by () sign around register
or memory.
 Effective Address of the Operand: (Ri) or (LOCA) is the contents of a register or
the memory location whose address appears in the instruction
ADD (R1), R2
Addr Memory
Contents
LOCA 0x1000 31
0x2000 2
R1 0x2000
R2 8
Addr Memory
Contents
LOCA 0x1000 31
0x2000 2
R1 0x2000
R2 10

Question
What will be the contents of the
 Register R1
 And Contents of the Memory location with address 0x1000 and 0x200
After executing the instruction ADD LOCA,(R1)
ADD LOCA, (R1)
Addr Memory
Contents
LOCA 0x1000 8
0x2000 2
R1 0x2000
Addr Memory
Contents
LOCA 0x1000 ??
0x2000 ??
R1 ??

Answer
 Register R1
After executing the instruction AD LOCA,(R1)
ADD LOCA, (R1)
Addr Memory
Contents
LOCA 0x1000 8
0x2000 2
R1 0x2000
Addr Memory
Contents
LOCA 0x1000 8
0x2000 10
R1 0x2000

Question
 Register R1
After executing the instruction ADD LOCA, R1
ADD LOCA, R1
Addr Memory
Contents
LOCA 0x1000 8
0x2000 2
R1 0x2000
Addr Memory
Contents
LOCA 0x1000 ??
0x2000 ??
R1 ??

Answer
 Register R1
After executing the instruction ADD LOCA, R1
ADD LOCA, R1
Addr Memory
Contents
LOCA 0x1000 8
0x2000 2
R1 0x2000
Addr Memory
Contents
LOCA 0x1000 8
0x2000 2
R1 0x2008

Index Addressing Mode
 The effective address of the operand is generated by adding a constant value to
the contents of a register specified in the instruction. The register in this case is
called as Index register.
 The operation is indicated as X(Ri).
 Effective Address of the Operand: X+Ri where X is a constant value (signed
integer) and Ri is the index register.
ADD 5(R1), R2
Addr Memory
Contents
0x2005 2
R1 0x2000
R2 8
Addr Memory
Contents
0x2005 2
R1 0x2000
R2 10

Index Addressing Mode
 The effective address of the operand is generated by adding a constant value to
the contents of a register specified in the instruction. The register in this case is
called as Index register.
 The operation is indicated as X(Ri).
 Effective Address of the Operand: X+Ri where X is a constant value (signed
integer) and Ri is the index register.
ADD 3(R1, R3), R2
Addr Memory
Contents
0x2005 6
R1 0x2000
R2 8
R3 2
Addr Memory
Contents
0x2005 6
R1 0x2000
R2 14
R3 2

Relative Addressing Mode
 In this mode the content of the program counter is added to the
address part of the instruction to obtain the effective address.
 Effective Address : X+PC where X is a constant value (signed integer)
and PC is the contents of the program counter.
Before Executing the JMP Instruction After Executing the JMP Instruction
Address
Move R1, R2 0x2000
JMP Next 0x2004
.
.
Next: Add R4, R6 0x2020
PC 0x2020
Memory
4 Bytes
Address
Move R1, R2 0x2000
JMP Next 0x2004
.
.
Next: Add R4, R6 0x2020
PC 0x2004
Memory
4 Bytes

Autoincrement Addressing Mode
 This is indirect mode with a modification. The effective address
of the operand is the contents of a pointer register specified in
the instruction. After accessing the operand, the contents of
this pointer register is incremented automatically to point to
the next entity.
 The mode is denoted by (Ri)+, where Ri is the pointer register.
 The + sign indicates that Ri is incremented after the operation.
 The increment operation is depending on the size of the
accessed operand. Thus, the increment value is 1 for byte-size
operands, 2 for word-size (16-bit) operands and 4 for long-
word (32-bit) operands.
 This mode is useful when operands are stored consecutively in
memory i.e., for array manipulation

 Example for Autoincrment Addressing Mode
Memory
4 Bytes
Move (R1)+, R2
Address
Memory
Contents
0x3000 6
0x3004 5
R1 0x3000
R2 20
Memory
4 Bytes
Address
Memory
Contents
0x3000 6
0x3004 5
R1 0x3004
R2 6

Question
What will be contents of Register R1 after executing the following
instruction ?
Memory
2 Bytes
Move (R1)+, R2
Address
Memory
Contents
0x3000 6
0x3002 5
R1 0x3000
R2 20
Memory
2 Bytes
Address
Memory
Contents
0x3000 6
0x3002 5
R1 ??
R2 6

Answer
instruction ?
Memory
2 Bytes
Move (R1)+, R2
Address
Memory
Contents
0x3000 6
0x3002 5
R1 0x3000
R2 20
Memory
2 Bytes
Address
Memory
Contents
0x3000 6
0x3002 5
R1 0x3002
R2 6

Autodecrement Addressing Mode
 This mode is useful to access an array in the reverse order.
The value of the pointer register specified in the instruction is
decremented first and this value is used as the effective
address of the operand.
 The mode is denoted by -(Ri), where Ri is the pointer register.
 The - sign indicates that Ri is decremented before accessing
the operand.
 The decrement operation is depending on the size of the
accessed operand. Thus, the decrement value is 1 for byte-size
operands, 2 for word-size (16-bit) operands and 4 for long-
word (32-bit) operands.
 This two modes (Autoincrement and Autodecrement) are
useful to implement a data structure called Stack.

Autodecrement Addressing Mode
 Example for Autodecrment Addressing Mode
Memory
4 Bytes
Move -(R1), R2
Address
Memory
Contents
0x3000 6
0x3004 5
R1 0x3004
R2 20
Memory
4 Bytes
Address
Memory
Contents
0x3000 6
0x3004 5
R1 0x3000
R2 6

Question
instruction ?
Memory
2 Bytes
Move -(R1), R2
Address
Memory
Contents
0x3000 6
0x3002 5
R1 0x3002
R2 20
Memory
2 Bytes
Address
Memory
Contents
0x3000 6
0x3002 5
R1 ??
R2 6

Answer
instruction ?
Memory
2 Bytes
Move -(R1), R2
Address
Memory
Contents
0x3000 6
0x3002 5
R1 0x3002
R2 20
Memory
2 Bytes
Address
Memory
Contents
0x3000 6
0x3002 5
R1 0x3000
R2 6

Question
What does the symbol '#' represent in
the instruction MOV #55H, A ?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype

Immediate
What does the symbol '#' represent in
the instruction MOV #55H, A ?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype

Question
In which addressing mode, the operand
is fetched from memory
a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

Answer
In which addressing mode, the operand
is fetched from memory
a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

Question
The addressing mode used in the instruction
Move 8(R2), R1 is
a. Index and Register
b. Direct and Register
c. Autoincrement and Register
d. Immediate and Register

Answer
Move 8(R2), R1 is

Question
Register R1 of the computer contain decimal value 1200.
What is the effective address of the source operand for the
instruction Load 20(R1),R5 . Assume instruction Format
“Load SourceOperand, DestinationOperand”.

Answer
Register R1 of computer contain decimal value 1200. What
is the effective address of the source operand for the
instruction Load 20(R1),R5 . Assume instruction Format
“Load SourceOperand, DestinationOperand”.
Effective Address: 1220

Question
Register R1 and R2 of computer contains the decimal value 1200
and 4600. What is the effective address of the destination operand
for the instruction
Store R5,30(R1,R2)
Assume instruction Format
“Store SourceOperand, DestinationOperand”

Answer
Register R1 and R2 of computer contains the decimal value 1200
and 4600. What is the effective address of the destination operand
for the instruction
Store R5,30(R1,R2)
Assume instruction Format
“Store SourceOperand, DestinationOperand”
Effective Address: 5830=30+1200+4600

Question
Move (R2)+, R1 is

Answer
Move (R2)+, R1 is

Homework Problem
Registers R1 and R2 of a computer contain the decimal values 1200 and
4600. What is the effective address of the memory operand in each of the
following instructions?
(a) Load 20(R1),R5
(b) Move #3000,R5
(c) Store R5,30(R1,R2)
(d) Add −(R2),R5
(e) Subtract (R1)+,R5

Answer
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is
the effective address of the memory operand in each of the following instructions?
(a) Load 20(R1),R5
(b) Move #3000,R5
(d) Add −(R2),R5
(e) Subtract (R1)+,R5
(a) Load 20(R1),R5
(b) Move #3000,R5
Effective Address: Operand value part of the instruction
(d) Add −(R2),R5
(v) Subtract (R1)+,R5

Writing Assembly Language programs
Program to find sum of n numbers

Assembly Language program to add n numbers
A straight-line program
for adding n numbers
Using a loop to add n numbers
Branching

Decrement and Increment Instructions
Example:
Decrement R1 ; Reduces the contents of register R1 by 1
Increment R1 ;Increment the contents of register R1 by 1

Conditional Codes
 The processor keeps track of information about the results of
various operations. This is accomplished by recording the
required information in individual bits, called Conditional flags.
 These flags are grouped together in a special processor
register called the condition code register (or status register)
 Four commonly used flags are:
1. N (Negative) set to 1 if the result is negative, otherwise cleared to 0
2. Z (zero) set to 1 if the result is 0; otherwise cleared to 0
3. V (Overflow) set to 1 if arithmetic overflow occurs; otherwise cleared to 0
4. C (Carry) set to 1 if a carry-out results from the operation; otherwise
cleared to 0

Example of Condition Codes
Consider 5-bit,
Signed 2’s Complement representation
A: 00101 (5)
B: 01010 (10)
A: 00101
+(B): 01010
01111
C = 0
N = 0
V = 0
Z = 0
Four commonly used flags are:
N (Negative) set to 1 if the result is negative, otherwise cleared to 0
Z (zero) set to 1 if the result is 0; otherwise cleared to 0
V (Overflow) set to 1 if arithmetic overflow occurs; otherwise cleared to 0
C (Carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0

Consider 5-bit,
A: 00111 (7)
B: 01101 (13)
A: 00111
-(B): 10011
11010
C = 0
N = 1
V = 0
Z = 0

Consider 5-bit,
A: 00111 (7)
B: 00111 (7)
A: 00111
-(B): 11001
00000
C = 1
N = 0
V = 0
Z = 1

Consider 5-bit,
A: 00111 (7)
B: 01101 (13)
A: 00111
+(B): 01101
10100
C = 0
N = 1
V = 1
Z = 0

Conditional Branching
Example of Conditional branch instruction
Branch>0 LOOP ;Branch if greater than zero
Is a conditional branch instruction that causes a branch to location LOOP if
the result of the immediately preceding instructions, is greater than zero.

Program to add n numbers using looping
Memory
4 Bytes

Address
N 4 1000
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
Memory
4 Bytes
Address
Move N,R1 3000
Move #Num1,R2 3004
Clear R0 3008
Loop: Add (R2), R0 3012
Add #4,R2 3016
Decrement R1 3020
Branch>0 Loop 3024
Move R0, Sum 3028
3032

Address
N 4 1000
Sum 16 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
Memory
4 Bytes
Address
Move N,R1 3000
Move #Num1,R2 3004
Clear R0 3008
Loop: Add (R2), R0 3012
Add #4,R2 3016
Decrement R1 3020
Branch>0 Loop 3024
Move R0, Sum 3028
3032
After Executing the Program

 Example for Autoincrment Addressing Mode
Memory
4 Bytes
Move (R1)+, R2
Address
Memory
Contents
0x3000 6
0x3004 5
R1 0x3000
R2 20
Memory
4 Bytes
Address
Memory
Contents
0x3000 6
0x3004 5
R1 0x3004
R2 6

Question
Modify the following program to add n numbers using looping,
but access the elements of the array using Autoincrement addressing mode
Address
N 4 1000
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
Memory
4 Bytes
Address
Move N,R1 3000
Move #Num1,R2 3004
Clear R0 3008
Loop: Add (R2), R0 3012
Add #4,R2 3016
Decrement R1 3020
Branch>0 Loop 3024
Move R0, Sum 3028
3032

Answer
Program to add n numbers using looping.
Accessing the elements of the array using Autoincrement addressing mode
Address
N 4 1000
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
Memory
4 Bytes
Address
Move N,R1 3000
Move #Num1,R2 3004
Clear R0 3008
Loop: Add (R2)+, R0 3012
Decrement R1 3016
Branch>0 Loop 3020
Move R0, Sum 3024
3028
3032

Program to find sum of Test1, Test2 and Test3
marks of all students
Address
N 2 1000
List BM01 1004 Student ID
1 1008 Test1 Marks
2 1012 Test2 Marks
3 1016 Test3 Marks
BM02 1020 Student ID
10 1024 Test1 Marks
20 1028 Test2 Marks
30 1032 Test3 Marks
Sum1 1036
Sum2 1040
Sum3 1044
Memory
4 Bytes

Program to find sum of Test1, Test2 and Test3
marks of all students
Address
N 2 1000
1 1008 Test1 Marks
2 1012 Test2 Marks
3 1016 Test3 Marks
10 1024 Test1 Marks
20 1028 Test2 Marks
30 1032 Test3 Marks
Sum1 1036
Sum2 1040
Sum3 1044
Memory
4 Bytes
Address
Move #List,R0 3000
Clear R1 3004
Clear R2 3008
Clear R3 3012
Move N,R4 3016
Loop: Add 4(R0), R1 3020
Add 8(R0), R2 3024
Add 12(R0), R3 3028
Add #16,R2 3032
Decrement R4 3036
Branch>0 Loop 3040
Move R1, Sum1 3044
Move R2, Sum2 3048
Move R3, Sum3 3052

After executing program
Address
N 2 1000
1 1008 Test1 Marks
2 1012 Test2 Marks
3 1016 Test3 Marks
10 1024 Test1 Marks
20 1028 Test2 Marks
30 1032 Test3 Marks
Sum1 11 1036
Sum2 22 1040
Sum3 33 1044
Memory
4 Bytes
Address
Move #List,R0 3000
Clear R1 3004
Clear R2 3008
Clear R3 3012
Move N,R4 3016
Loop: Add 4(R0), R1 3020
Add 8(R0), R2 3024
Add 12(R0), R3 3028
Add #16,R2 3032
Decrement R4 3036
Branch>0 Loop 3040
Move R1, Sum1 3044
Move R2, Sum2 3048
Move R3, Sum3 3052

Question
The list of student marks as shown in figure has been used to contain test scores for
each student. Assume that there are n students. Write an assembly language program
for computing the sums of the scores on each test and store these sums in the
memory word locations at addresses SUM, SUM+4, SUM+8,...... The type of program
shown in figure works for the 3-test cases. But now using two nested loops i.e., the
inner loop should accumulate the sum for a particular test of all students, and the
outer loop should run over the number of tests, j. Assume that j is stored in memory
location J, placed ahead of location N.

Answer
Memory word location J contains the number of tests, j, and memory word location N
contains the number of students, n. The list of student marks begins at memory word
location LIST in the format shown in Figure . The parameter Stride = 4(j + 1) is the
distance in bytes between scores on a particular test for adjacent students in the list.
The Base with index addressing mode (R1,R2) is used to access the scores on a
particular test. Register R1 points to the test score for student 1, and R2 is
incremented by Stride in the inner loop to access scores on the same test by
successive students in the list.

Answer

Question
Can the program given will work find the sum of test scores of all
students if we increase the number of tests to four

Answer
Can the program given will work find the sum of test scores of all
students if we increase the number of tests to four: Yes

Stacks and Queues

Stack
 A stack is a special type of data structure where elements are
inserted from one end and elements are deleted from the same
end. This end is called the top of the stack
 The various operations performed on stack:
 Insert: An element is inserted from top end. Insertion operation is called
push operation.
 Delete: An element is deleted from top end. Deletion operation is called pop
operation.
 A processor-register is used to keep track of the address of the
element of the stack that is at the top at any given time. This
register is called the Stack Pointer.
 If we assume a byte-addressable memory with 32-bit word
length
 The Push operation can be implemented as
Subtract #4,SP
Move NEWITEM,(SP)
 The Pop operation can be implemented as
Move (SP), ITEM
Subtract #4,SP

Stack: Push Operation Implementation
Memory
4 Bytes
Subtract #4,SP
Move NEWITEM,(SP)
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004
3012
3016
3020
SP 3024
Memory
4 Bytes
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004
3012
3016
3020 6
SP 3020
SP

Stack: Push Operation Implementation
Memory
4 Bytes
Subtract #4,SP
Move NEWITEM,(SP)
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004
3012
3016
3020
SP 3024
Memory
4 Bytes
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004
3012
3016
3020 6
SP 3020
SP
Move NEWITEM,-(SP)
(OR)

Stack: Pop Operation Implementation
Memory
4 Bytes
Move (SP), ITEM
Add #4,SP
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004
3012
3016
3020 6
SP 3020
Memory
4 Bytes
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004 6
3012
3016
3020 6
SP 3024
SP
SP

Stack: Pop Operation Implementation
Memory
4 Bytes
Move (SP), ITEM
Add #4,SP
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004
3012
3016
3020 6
SP 3020
Memory
4 Bytes
Address
Memory
Contents
NEWITEM 2000 6
ITEM 2004 6
3012
3016
3020 6
SP 3024
SP
SP
Move (SP)+, ITEM
(OR)

Question
Register R5 is used in a program to point to top of a stack. Consider each word length
in stack is of 32-bits.Write a sequence of instructions using the Index, Autoincrement
and Autodecrement addressing modes to perform each of the following
a. Pop the top two items off the stack, add them and then push the result onto the
stack.
b. Copy the fifth item from the top into register R3
c. Remove the top ten items from stack
Address Memory Contents
3000 10
3004 20
3008 30
3012 40
3016 50
3020 60
3024 70
3028 80
3032 90
3036 100
3040
4 Bytes
R5

Answer
stack.
Answer
(a)
Move (R5)+,R0
Add (R5)+,R0
Move R0,-(R5)
3000 10
3004 20
3008 30
3012 40
3016 50
3020 60
3024 70
3028 80
3032 90
3036 100
3040
4 Bytes
R5

Answer
stack.
Answer
Answer
(b)
Move 16(R5),R3
3000 10
3004 20
3008 30
3012 40
3016 50
3020 60
3024 70
3028 80
3032 90
3036 100
3040
4 Bytes
R5

Answer
stack.
Answer
(c)
Add #40,R5
3000 10
3004 20
3008 30
3012 40
3016 50
3020 60
3024 70
3028 80
3032 90
3036 100
3040
4 Bytes
R5

Queues

Subroutines

Subroutine to Program to add n numbers
using looping
Address
N 4 1000
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
Memory
4 Bytes
Subroutine
LISTADD Address
Clear R0 2000
Loop: Add (R2)+, R0 2004
Decrement R1 2008
Branch>0 Loop 2012
Return 2016
Address
Main
Program
3000 Move N,R1
3004 Move #Num1,R2
3008 Call LISTADD
3012 Move R0, Sum

Question

Illustration with Example
Address
A(0,0) 1 1000
A(0,1) 2 1004
A(0,2) 3 1008
A(1,0) 10 1012
A(1,2) 20 1016
A(2,2) 30 1020
Memory
4 Bytes Col-0 Col-1 Col-2
Row-0 1 2 3
Row-1 10 20 30
Col-0 Col-1 Col-2
Row-0 1 2 5
Row-1 10 20 50
Col-x (1) +
Col-y (2)

Answer
Assume that the subroutine can change the contents of any register used to
pass parameters.

Subroutine Nestng

Subroutines: Parameter Passing
 The exchange of information between a calling
program and a subroutine is referred to as
Parameter passing.
 The parameters may be passed using
 Registers
 Memory Location
 Stack

Subroutine: Passing of Parameters through
Registers
Address
N 4 1000
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
Memory
4 Bytes
Subroutine
LISTADD Address
Clear R0 2000
Loop: Add (R2)+, R0 2004
Decrement R1 2008
Branch>0 Loop 2012
Return 2016
Address
Main
Program
3000 Move N,R1
3004 Move #Num1,R2
3008 Call LISTADD
3012 Move R0, Sum
In calling program,
Register R1 and R2 is used to pass the parameters N and
address of Num1 location
- N is passed using: Pass by Value
- Address of Num1 is passed using: Pass by Reference.
The called Subroutine: LISTADD, returns the parameter
total value through the register R0

Subroutine: Passing of Parameters through Stack
Address
N 3 1000
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Memory
4 Bytes
Subroutine
LISTADD Address
Move R0,-(SP) 2000
Move R1,-(SP) 2004
Move R2,-(SP) 2008
Move 16(SP), R1 2012
Move 20(SP), R2 2016
Clear R0 2020
Loop: Add (R2)+, R0 2024
Decrement R1 2028
Branch>0 Loop 2032
Move R0,20(SP) 2036
Move (SP)+, R2 2040
Move (SP)+, R1 2044
Move (SP)+, R0 2048
Return 2052
Address
Main
Program
3000 Move #Num1,-(SP)
3004 Move N, -(SP)
3008 Call LISTADD
3012 Move 4(SP), Sum
3014 Add #8, SP

Subroutine: Passing of Parameters through Stack
 Stack contents for the program shown in previous slide.
Call instruction pushes return address on to stack.

Shift and Rotate Instructions

Shift Instructions
Shift Instructions
Logical Arithmetic
Left Right
Left Right

Logical Left Shift Instruction
C 0
MSB LSB
Logical Left Shift
General Syntax: LShiftL Count, DestinationOperand
LShiftL #2, R1
0 1 0 1 0 1 1 0 1
R1
C
1 0 1 0 1 1 0 1 0
R1
C
After 1st Shift
0 1 0 1 1 0 1 0 0
R1
C
After 2nd Shift

Logical Right Shift Instruction
C
0
MSB LSB
Logical Right Shift
General Syntax: LShiftR Count, DestinationOperand
LShiftR #2, R1
0
1 0 1 0 1 1 0 1
R1 C
1
0 1 0 1 0 1 1 0
R1 C
After 1st Shift
0
0 0 1 0 1 0 1 1
R1 C
After 2nd Shift

Arithmetic Right Shift Instruction
C
MSB LSB
Arithmetic Right Shift
General Syntax: AShiftR Count, DestinationOperand
RShiftR #2, R1
0
1 0 1 0 1 1 0 1
R1 C
1
1 1 0 1 0 1 1 0
R1 C
After 1st Shift
0
R1 C
After 2nd Shift
1 1 1 0 1 0 1 1

Question
The content of a 4-bit register is initially
1101. The register is logically shifted 2
times to the right. What is the content
of the register after each shift?
a. 1110, 0111
b. 0001, 1000
c. 1101, 1011
d. 0110, 0011

Question
If a register containing data 11001100
is subjected to logical shift left operation
of 1 bit, then the content of the register
after 'LshiftL' shall be
a. 01100110
b. 10011001
c. 11011001
d. 10011000

Rotate Instructions
Rotate Instructions
With Carry Without Carry
Left Right
Left Right

Rotate Left with Carry
C
MSB LSB
General Syntax: RotateLC Count, DestinationOperand
RotateLC #1, R1
0 1 0 1 1 0 1 0 0
R1
C
1 0 1 1 0 1 0 0 0
R1
C

Rotate Left without Carry
C
MSB LSB
General Syntax: RotateL Count, DestinationOperand
RotateL #1, R1
0 1 0 1 1 0 1 0 0
R1
C
1 0 1 1 0 1 0 0 1
R1
C

Rotate Right with Carry
C
MSB LSB
General Syntax: RotateRC Count, DestinationOperand
RotateRC #1, R1
0
1 0 1 1 0 1 0 0
R1 C
0
0 1 0 1 1 0 1 0
R1 C

Rotate Right without Carry
C
MSB LSB
General Syntax: RotateR Count, DestinationOperand
RotateR #1, R1
0
1 0 1 1 0 1 0 0
R1 C
0
0 1 0 1 1 0 1 0
R1 C

Stack Frame
 Stack Frame refers to locations that constitute a private work-
space for the subroutines
 The work space is
 Created at the time the subroutine is entered and
 Freed up when the subroutine returns control to the calling program
Figure 2.27:
Subroutine stack
frame example

Frame Pointer and Operation on Stack Frame

Basic Input and Output Operations

Encoding of machine Instructions

Encoding of machine Instructions (Contd…)

Thanks for Listening
END of Unit-1 : Part2

To Do
 Match each of the high level language statements given
on the left hand side with the most natural addressing
mode from those listed on the right hand side.

To Do
Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then add them.
State whether or not overflow occurs in each case.
(a) 4 and 11
00100 + 01011 = 01111
4+11=15
(b) 6 and 14
00110 + 01110 = 10100 overflows
6 + 14 = 20
(c) −13 and 12
10011 + 011000 = 11111 (complement)
-13 + 12 = -1
(d) −4 and 8
11100 + 01000 = 00100
-4 + 8 = 4
(e) −2 and −9
11110 + 10111 = 10101
-2 + -9 = -11
(f ) −9 and −14
10111 + 10010 = 01001 overflows
-9 + -14 = -23

To Do
 What is the minimum number of bits that are required to
uniquely represent the characters of English alphabet?
(Consider upper case characters alone)
 How many more characters can be uniquely represented
without requiring additional bits?

To Do
The following binary numbers are 4-bit 2's complement binary numbers. Which of the
following operations generate overflow? Justify your answers by translating the
operands and results into decimal.

Describe what conditions indicate overflow has occurred
when two 2's complement numbers are added.
 When adding two numbers, overflow occurs when the
two operands have the same leftmost bit and the
leftmost bit of the answer is different.
 When the operands have differing leftmost bits, overflow
cannot occur when adding them together because we are
adding a positive number with a negative number which
means we are actually subtracting. It implies that the
result cannot be bigger than the operands. So there is no
possibility of overflow in this case. The leftmost bit is
frequently referred to as the Most Significant Bit (MSB
for short).

Example of 2’s Complement

Little-endian and Big-endian.
 Consider a 32 bit integer (in hex): 0xabcdef12. It consists of 4
bytes: ab, cd, ef, and 12. Hence this integer will occupy 4
bytes in memory. Say we store it at memory address starting
1000. There are 24 different orderings possible to store these
4 bytes in 4 locations (1000 - 1003). 2 among these 24
possibilities are very popular. These are called as little endian
and big endian.

20 1
21 2 2
22 2 * 2 4
23 2 * 2 * 2 8
24 2 * 2 * 2 * 2 16
25 2 * 2 * 2 * 2 * 2
32
26 2 * 2 * 2 * 2 * 2 * 2 64
27 2 * 2 * 2 * 2 * 2 * 2 * 2
128

Address
J 3 1000
N 2 1004
1 1012 Test1 Marks
2 1016 Test2 Marks
3 1020 Test3 Marks
10 1028 Test1 Marks
20 1032 Test2 Marks
30 1036 Test3 Marks
Sum 11 1040
m+4 22 1044
m+8 33 1046
Memory
4 Bytes
Address
Move #List,R0 3000
Clear R1 3004
Clear R2 3008
Clear R3 3012
Move N,R4 3016
Loop: Add 4(R0), R1 3020
Add 8(R0), R2 3024
Add 12(R0), R3 3028
Add #16,R2 3032
Decrement R4 3036
Branch>0 Loop 3040
Move R1, Sum1 3044
Move R2, Sum2 3048
Move R3, Sum3 3052

Address
J 4 1000
N 2 1004
1 1012 Test1 Marks
2 1016 Test2 Marks
3 1020 Test3 Marks
4 1024 Test4 Marks
10 1032 Test1 Marks
20 1036 Test2 Marks
30 1040 Test3 Marks
40 1044 Test4 Marks
Sum ?? 1046
m+4 ?? 1050
Memory
4 Bytes
Address
Move #List,R0 3000
Clear R1 3004
Clear R2 3008
Clear R3 3012
Move N,R4 3016
Loop: Add 4(R0), R1 3020
Add 8(R0), R2 3024
Add 12(R0), R3 3028
Add #16,R2 3032
Decrement R4 3036
Branch>0 Loop 3040
Move R1, Sum1 3044
Move R2, Sum2 3048
Move R3, Sum3 3052

Unit1_Part2-Machine_Instructions_Programs_7_9_2018_3pm.ppt

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to Unit1_Part2-Machine_Instructions_Programs_7_9_2018_3pm.ppt

Similar to Unit1_Part2-Machine_Instructions_Programs_7_9_2018_3pm.ppt (20)

More from ChiragSuresh

More from ChiragSuresh (9)

Recently uploaded

Recently uploaded (20)

Unit1_Part2-Machine_Instructions_Programs_7_9_2018_3pm.ppt

Editor's Notes