memory reference instruction

BY
SAKTHIPRIYA.V
NADAR SARASWATHI COLLEGE OF ARTS ANDSCIENCE

MRI DEFINITION:
To specify the microoperation needed for
the execution of the instruction.
An instruction in words in usually lengthy
and enough space is available in the table.
It is can be defined by means of register
transfer notation.

CONT..
Data are store in a memory can be
processed directly.
It must be read from memory to a register
can be operate in logic circuit.
In the lengthly explanation.

MEMORY REFERENCE
INSTRUCTION:
AND to AC
ADD to AC
LDA :load to AC
STA: store to AC
BUN: Branch Unconditionally
BSA: Branch and save return address
ISZ: Increment and skip if zero

SYMPOL OPERATION
DECODER
SYMBOLIC DESCRIPTION
AND D0 AC  AC ^ M[AR]
ADD D1 AC <- AC+M[AR], E <- Cout
LDA D2 AC <- M[AR]
STA D3 M[AR] <-AC
BUN D4 PC <- AR
BSA D5 M[AR]<- PC, PC<- AR+1
M[AR] <- M[AR]+1
ISZ D6 IF M[AR]+1=0 THEN
PC <- PC+1

AND TO AC:
It performs the AND logic operation in
AC, and the memory word specified by
the “effective address”.
D0T4:DR <- M[AR]
D0T5:AC <-AC ^DR,SC <-0
• The two timing signal are T4 ,T5.
• T4 transfer the operand from memory in
DR.

T5 transfer to AC result AND logic
operation.
T0 is to start a new instruction cycle.

ADD to AC:
 Adds the content of the memory word specified by the
effective addresses.
 Sum transferred to AC and output is carry(cout)
transfer to the E flip flop.
D1T4:DR<-M[AR]
D1T5:AC<-AC+DR,E<-COUT,SC<-0
 Two timing signals t4 and t5.decoder d1 instead d0
used in AND instruction
 Instruction fetched from memory and decoder.

 Two timing signals t4 and t5.decoder d1 instead d0
used in AND instruction
 Instruction fetched from memory and decoder.
 Output determine the sequence of microoperation
execution of a MRI.

LDA:LOAD to AC:
 Memory word specified by the effective addresses to
AC.
D2T4:DR<-M[AR]
D2T5:AC<-DR,SC<-0
 No direct path from the bus into AC.
 The adder and logic circuit receive information from
DR.transfer to AC.
 Read from memory and transfer to the adder and logic
circuit.

STA:-STORE AC:
 Memory word specified by the effective address.
 Output of AC is applied to the bus data input of
memory is connected to the execute the one
microoperation.
D3T4:M[AR]<-AC,SC<-0.

BUN:-BRANCH UNCONDITIONALLY:
 Instruction specified to the effective address.
 Pc holds the address of the instruction read from
memory in the next instruction cycle.
 The programmer specify an instruction out of
sequence.program branch unconditionally.
 Execute one microoperation.
D4T4 :PC<-AR,SC<-0
 EA from AR is transferred the common bus to PC.SC to
O transfer control to T0.

BSA :-BRANCH and SAVE RETURN
ADDRESS:
 Subroutine(or)procedure.
 Memory location specified by the effective address.
 Address of the first instruction in the subroutine.
M[AR]<-PC, PC<-AR+1.
 Next instruction is called return address.
M[135]<-21,PC<-135+1=136.
 BSA instruction performs the function usually referred
to as a subroutine call.

 End of the subroutine performs the function refer is called
subroutine return.
D5T4 :M[AR]<-PC,AR <-+1
D5T5 :PC<-AR,SC<-0
 Enable the INR input of AR.

Memory Memory
0 BSA 135
NEXT INSTRUCTION
Subroutine
1 BUN 135
0 BSA
135
Next instruction
21
subroutine
1 BUN
135

ISZ:-INCREMENT and SKIP it ZERO
 The instruction increment the word specified by the
effective address.
 INR value is 0,PC incremented by 1.
 It is stored in a negative number.so used to an 2’s
complements.negative number are incremented by 1.
 The instruction is a sequence of microoperation
D6T4:DR<-M[AR].
D6T5: DR<-DR+1.
D6T6:M[AR]<-DR ,if(DR=0)then (PC<-
PC+1),SC<-0.

CONTROL FLOW CHART:
 Show the execution of the microoperation in seven
memory reference instruction.
 It is preformed to the timing signals for T4,T5 or T6
the timing signals are operation code value.
 SC is the sequence counter and sc is cleared to 0.is
include to an last timing signal.
 The increment and skip is zero(ISZ).to there are
include three bits counter.

memory reference instruction

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