The document discusses the memory system in computers including main memory, cache memory, and different types of memory chips. It provides details on the following key points in 3 sentences:
The document discusses the different levels of memory hierarchy including main memory, cache memory, and auxiliary memory. It describes the basic concepts of memory including addressing schemes, memory access time, and memory cycle time. Examples of different types of memory chips are discussed such as SRAM, DRAM, ROM, and cache memory organization and mapping techniques.
Memory organization in computer architectureFaisal Hussain
Memory organization in computer architecture
Volatile Memory
Non-Volatile Memory
Memory Hierarchy
Memory Access Methods
Random Access
Sequential Access
Direct Access
Main Memory
DRAM
SRAM
NVRAM
RAM: Random Access Memory
ROM: Read Only Memory
Auxiliary Memory
Cache Memory
Hit Ratio
Associative Memory
Memory is organized in a hierarchy with different levels providing trade-offs between speed and cost.
- Cache memory sits between the CPU and main memory for fastest access.
- Main memory (RAM) is where active programs and data reside and is faster than auxiliary memory but more expensive.
- Auxiliary memory (disks, tapes) provides backup storage and is slower than main memory but larger and cheaper.
Virtual memory manages this hierarchy through address translation techniques like paging that map virtual addresses to physical locations, allowing programs to access more memory than physically available. When data is needed from auxiliary memory a page fault occurs and page replacement algorithms determine what data to remove from main memory.
This document discusses asynchronous data transfer between independent units. It describes two methods for asynchronous transfer - strobe control and handshaking. Strobe control uses a single control line to time each transfer, while handshaking introduces a second control signal to provide confirmation between units. Specifically, it details the handshaking process, which involves control signals like "data valid" and "data accepted" or "ready for data" to coordinate placing data on the bus and accepting data between a source and destination unit.
Cache memory is a small, fast memory located between the CPU and main memory. It stores copies of frequently used instructions and data to accelerate access and improve performance. There are different mapping techniques for cache including direct mapping, associative mapping, and set associative mapping. When the cache is full, replacement algorithms like LRU and FIFO are used to determine which content to remove. The cache can write to main memory using either a write-through or write-back policy.
The document discusses various methods for input/output (IO) in computer systems, including IO interfaces, programmed IO, interrupt-initiated IO, direct memory access (DMA), and input-output processors (IOPs). It describes how each method facilitates the transfer of data between the CPU, memory, and external IO devices.
The 8237 DMA controller allows data transfer between I/O devices and memory without CPU intervention. It uses HOLD and HLDA signals to request and acknowledge DMA actions from the CPU. The 8237 contains registers like CAR, CWCR, CR, and SR to program DMA channel operations, addresses, counts, and status. It can perform DMA transfers at up to 1.6 MB/s across 4 channels. Modern systems integrate DMA controllers within chipsets rather than using discrete 8237 components.
The DMA controller (8257) allows data transfer between I/O devices and memory without CPU involvement. It has 4 independent channels that can be programmed to transfer data via DMA read, write, or verify operations. The 8257 interfaces with the 8085 microprocessor by controlling address/data buses and generating control signals during DMA cycles when it acts as the bus master.
The document discusses the memory system in computers including main memory, cache memory, and different types of memory chips. It provides details on the following key points in 3 sentences:
The document discusses the different levels of memory hierarchy including main memory, cache memory, and auxiliary memory. It describes the basic concepts of memory including addressing schemes, memory access time, and memory cycle time. Examples of different types of memory chips are discussed such as SRAM, DRAM, ROM, and cache memory organization and mapping techniques.
Memory organization in computer architectureFaisal Hussain
Memory organization in computer architecture
Volatile Memory
Non-Volatile Memory
Memory Hierarchy
Memory Access Methods
Random Access
Sequential Access
Direct Access
Main Memory
DRAM
SRAM
NVRAM
RAM: Random Access Memory
ROM: Read Only Memory
Auxiliary Memory
Cache Memory
Hit Ratio
Associative Memory
Memory is organized in a hierarchy with different levels providing trade-offs between speed and cost.
- Cache memory sits between the CPU and main memory for fastest access.
- Main memory (RAM) is where active programs and data reside and is faster than auxiliary memory but more expensive.
- Auxiliary memory (disks, tapes) provides backup storage and is slower than main memory but larger and cheaper.
Virtual memory manages this hierarchy through address translation techniques like paging that map virtual addresses to physical locations, allowing programs to access more memory than physically available. When data is needed from auxiliary memory a page fault occurs and page replacement algorithms determine what data to remove from main memory.
This document discusses asynchronous data transfer between independent units. It describes two methods for asynchronous transfer - strobe control and handshaking. Strobe control uses a single control line to time each transfer, while handshaking introduces a second control signal to provide confirmation between units. Specifically, it details the handshaking process, which involves control signals like "data valid" and "data accepted" or "ready for data" to coordinate placing data on the bus and accepting data between a source and destination unit.
Cache memory is a small, fast memory located between the CPU and main memory. It stores copies of frequently used instructions and data to accelerate access and improve performance. There are different mapping techniques for cache including direct mapping, associative mapping, and set associative mapping. When the cache is full, replacement algorithms like LRU and FIFO are used to determine which content to remove. The cache can write to main memory using either a write-through or write-back policy.
The document discusses various methods for input/output (IO) in computer systems, including IO interfaces, programmed IO, interrupt-initiated IO, direct memory access (DMA), and input-output processors (IOPs). It describes how each method facilitates the transfer of data between the CPU, memory, and external IO devices.
The 8237 DMA controller allows data transfer between I/O devices and memory without CPU intervention. It uses HOLD and HLDA signals to request and acknowledge DMA actions from the CPU. The 8237 contains registers like CAR, CWCR, CR, and SR to program DMA channel operations, addresses, counts, and status. It can perform DMA transfers at up to 1.6 MB/s across 4 channels. Modern systems integrate DMA controllers within chipsets rather than using discrete 8237 components.
The DMA controller (8257) allows data transfer between I/O devices and memory without CPU involvement. It has 4 independent channels that can be programmed to transfer data via DMA read, write, or verify operations. The 8257 interfaces with the 8085 microprocessor by controlling address/data buses and generating control signals during DMA cycles when it acts as the bus master.
Direct memory access (DMA) allows certain hardware subsystems to access computer memory independently of the central processing unit (CPU). During DMA transfer, the CPU is idle while an I/O device reads from or writes directly to memory using a DMA controller. This improves data transfer speeds as the CPU does not need to manage each memory access and can perform other tasks. DMA is useful when CPU cannot keep up with data transfer speeds or needs to work while waiting for a slow I/O operation to complete.
This document discusses different types of data transfer modes between I/O devices and memory, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It explains that DMA allows I/O devices to access memory directly without CPU intervention by using a DMA controller. The basic operations of DMA include the DMA controller gaining control of the system bus, transferring data directly between memory and I/O devices by updating address and count registers, and then relinquishing control back to the CPU. Different DMA transfer techniques like byte stealing, burst, and continuous modes are also covered.
Memory organisation ppt final presentationrockymani
Memory is an essential component of computers that is used to store programs and data. Computers typically have three levels of memory: main memory, secondary memory, and cache memory. Main memory is fast memory that stores programs and data being executed. Secondary memory is permanent storage for programs and data used less frequently. Cache memory sits between the CPU and main memory for faster access. Memory is also classified by location, access method, volatility, and type. The different types include registers, main memory, secondary memory, cache memory, RAM, ROM, PROM, EPROM, and EEPROM.
About Cache Memory
working of cache memory
levels of cache memory
mapping techniques for cache memory
1. direct mapping techniques
2. Fully associative mapping techniques
3. set associative mapping techniques
Cache memroy organization
cache coherency
every thing in detail
The document provides an overview of instruction sets, including:
1) Instruction formats contain operation codes, source/result operand references, and next instruction references. Operands can be located in memory, registers, or immediately within the instruction.
2) Types of operations include data transfer, arithmetic, logical, conversion, I/O, system control, and transfer of control.
3) Addressing modes specify how the target address is identified in the instruction, such as immediate, direct, indirect, register, register indirect, displacement, and stack addressing.
This document discusses computer registers and their functions. It describes 8 key registers - Data Register, Address Register, Accumulator, Instruction Register, Program Counter, Temporary Register, Input Register and Output Register. It explains what each register stores and its role. For example, the Program Counter holds the address of the next instruction to be executed, while the Accumulator is used for general processing. The registers are connected via a common bus to transfer information between memory and registers for processing instructions.
This document discusses memory interfacing with the 8085 microprocessor. It begins by describing the different types of computer memory, including primary/volatile memory (RAM and ROM) and secondary/non-volatile memory (magnetic tapes, disks, optical disks). It then discusses how the 8085 microprocessor interfaces with memory chips through an interface circuit. The interface circuit matches the memory chip signals to the microprocessor address and control signals. Memory interfacing involves selecting the appropriate memory chip, identifying the correct register using address lines, and enabling read/write buffers using control signals.
Cache memory is a small, fast memory located close to the processor that stores frequently accessed data from main memory. When the processor requests data, the cache is checked first. If the data is present, there is a cache hit and the data is accessed quickly from the cache. If not present, there is a cache hit and the data must be fetched from main memory, which takes longer. Cache memory relies on principles of temporal and spatial locality, where frequently and nearby accessed data is likely to be needed again soon. Mapping functions like direct, associative, and set-associative mapping determine how data is stored in the cache. Replacement policies like FIFO, LRU, etc. determine which cached data gets replaced when new
The document discusses cache memory and provides information on various aspects of cache memory including:
- Introduction to cache memory including its purpose and levels.
- Cache structure and organization including cache row entries, cache blocks, and mapping techniques.
- Performance of cache memory including factors like cycle count and hit ratio.
- Cache coherence in multiprocessor systems and coherence protocols.
- Synchronization mechanisms used in multiprocessor systems for cache coherence.
- Paging techniques used in cache memory including address translation using page tables and TLBs.
- Replacement algorithms used to determine which cache blocks to replace when the cache is full.
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
- A key objective of computer systems is achieving high performance at low cost, measured by price/performance ratio.
- Processor performance depends on how fast instructions can be fetched from memory and executed.
- Caches improve performance by storing recently accessed data from main memory closer to the processor, reducing access time compared to main memory. This can increase hit rates but requires managing cache misses and write policies.
This document discusses the memory hierarchy in computers. It begins by explaining that computer memory is organized in a pyramid structure from fastest and smallest memory (cache) to slower and larger auxiliary memory. The main types of memory discussed are RAM, ROM, cache memory, and auxiliary storage. RAM is further divided into SRAM and DRAM. The document provides details on the characteristics of each memory type including access speed, volatility, capacity and cost. Diagrams are included to illustrate concepts like RAM, ROM, cache levels and auxiliary devices. Virtual memory is also briefly introduced at the end.
The document discusses the concept of virtual memory. Virtual memory allows a program to access more memory than what is physically available in RAM by storing unused portions of the program on disk. When a program requests data that is not currently in RAM, it triggers a page fault that causes the needed page to be swapped from disk into RAM. This allows the illusion of more memory than physically available through swapping pages between RAM and disk as needed by the program during execution.
1) The document discusses different types of micro-operations including arithmetic, logic, shift, and register transfer micro-operations.
2) It provides examples of common arithmetic operations like addition, subtraction, increment, and decrement. It also describes logic operations like AND, OR, XOR, and complement.
3) Shift micro-operations include logical shifts, circular shifts, and arithmetic shifts which affect the serial input differently.
Basic Computer Organization and Design
.....................................................................
The basic computer design represents all of the major concepts in CPU design without overwhelming students with the complexity of a modern commercial CPU.
The document discusses the memory hierarchy in computers. It describes the different levels of memory from fastest to slowest as register memory, cache memory, main memory (RAM and ROM), and auxiliary memory (magnetic tapes, hard disks, etc.). The main memory directly communicates with the CPU while the auxiliary memory provides backup storage and needs to transfer data to main memory to be accessed by the CPU. A cache memory is also used to increase processing speed.
Control Units : Microprogrammed and Hardwired:control unitabdosaidgkv
The document discusses control units in CPUs. There are two main methods for implementing control units: hardwired and microprogrammed. A hardwired control unit generates control signals through circuitry using logic gates, while a microprogrammed control unit generates control signals by executing a stored microprogram. Overall, hardwired control units are faster but less flexible, while microprogrammed control units are slower but more flexible and modifiable.
The document discusses various aspects of I/O organization in a computer system. It describes the input-output interface that provides a method for transferring information between internal storage and external I/O devices. It discusses asynchronous data transfer techniques like strobe control and handshaking. It also covers asynchronous serial transmission, different modes of data transfer like programmed I/O, interrupt-initiated I/O, and direct memory access (DMA).
Associative memory, also known as content-addressable memory (CAM), allows data to be searched based on its content rather than its location. It consists of a memory array, argument register (containing the search word), key register (specifying which bits to compare), and match register (indicating matching locations). All comparisons are done in parallel. Associative memory provides faster searching than conventional memory but is more expensive due to the additional comparison circuitry in each cell. It is well-suited for applications requiring very fast searching such as databases and virtual memory address translation.
The document discusses different levels of computer memory organization. It describes the memory hierarchy from fastest to slowest as registers, cache memory, main memory, and auxiliary memory such as magnetic disks and tapes. It explains how each level of memory trades off speed versus cost and capacity. The document also covers virtual memory and how it allows programs to access large logical addresses while physical memory remains small.
Direct memory access (DMA) allows certain hardware subsystems to access computer memory independently of the central processing unit (CPU). During DMA transfer, the CPU is idle while an I/O device reads from or writes directly to memory using a DMA controller. This improves data transfer speeds as the CPU does not need to manage each memory access and can perform other tasks. DMA is useful when CPU cannot keep up with data transfer speeds or needs to work while waiting for a slow I/O operation to complete.
This document discusses different types of data transfer modes between I/O devices and memory, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It explains that DMA allows I/O devices to access memory directly without CPU intervention by using a DMA controller. The basic operations of DMA include the DMA controller gaining control of the system bus, transferring data directly between memory and I/O devices by updating address and count registers, and then relinquishing control back to the CPU. Different DMA transfer techniques like byte stealing, burst, and continuous modes are also covered.
Memory organisation ppt final presentationrockymani
Memory is an essential component of computers that is used to store programs and data. Computers typically have three levels of memory: main memory, secondary memory, and cache memory. Main memory is fast memory that stores programs and data being executed. Secondary memory is permanent storage for programs and data used less frequently. Cache memory sits between the CPU and main memory for faster access. Memory is also classified by location, access method, volatility, and type. The different types include registers, main memory, secondary memory, cache memory, RAM, ROM, PROM, EPROM, and EEPROM.
About Cache Memory
working of cache memory
levels of cache memory
mapping techniques for cache memory
1. direct mapping techniques
2. Fully associative mapping techniques
3. set associative mapping techniques
Cache memroy organization
cache coherency
every thing in detail
The document provides an overview of instruction sets, including:
1) Instruction formats contain operation codes, source/result operand references, and next instruction references. Operands can be located in memory, registers, or immediately within the instruction.
2) Types of operations include data transfer, arithmetic, logical, conversion, I/O, system control, and transfer of control.
3) Addressing modes specify how the target address is identified in the instruction, such as immediate, direct, indirect, register, register indirect, displacement, and stack addressing.
This document discusses computer registers and their functions. It describes 8 key registers - Data Register, Address Register, Accumulator, Instruction Register, Program Counter, Temporary Register, Input Register and Output Register. It explains what each register stores and its role. For example, the Program Counter holds the address of the next instruction to be executed, while the Accumulator is used for general processing. The registers are connected via a common bus to transfer information between memory and registers for processing instructions.
This document discusses memory interfacing with the 8085 microprocessor. It begins by describing the different types of computer memory, including primary/volatile memory (RAM and ROM) and secondary/non-volatile memory (magnetic tapes, disks, optical disks). It then discusses how the 8085 microprocessor interfaces with memory chips through an interface circuit. The interface circuit matches the memory chip signals to the microprocessor address and control signals. Memory interfacing involves selecting the appropriate memory chip, identifying the correct register using address lines, and enabling read/write buffers using control signals.
Cache memory is a small, fast memory located close to the processor that stores frequently accessed data from main memory. When the processor requests data, the cache is checked first. If the data is present, there is a cache hit and the data is accessed quickly from the cache. If not present, there is a cache hit and the data must be fetched from main memory, which takes longer. Cache memory relies on principles of temporal and spatial locality, where frequently and nearby accessed data is likely to be needed again soon. Mapping functions like direct, associative, and set-associative mapping determine how data is stored in the cache. Replacement policies like FIFO, LRU, etc. determine which cached data gets replaced when new
The document discusses cache memory and provides information on various aspects of cache memory including:
- Introduction to cache memory including its purpose and levels.
- Cache structure and organization including cache row entries, cache blocks, and mapping techniques.
- Performance of cache memory including factors like cycle count and hit ratio.
- Cache coherence in multiprocessor systems and coherence protocols.
- Synchronization mechanisms used in multiprocessor systems for cache coherence.
- Paging techniques used in cache memory including address translation using page tables and TLBs.
- Replacement algorithms used to determine which cache blocks to replace when the cache is full.
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
- A key objective of computer systems is achieving high performance at low cost, measured by price/performance ratio.
- Processor performance depends on how fast instructions can be fetched from memory and executed.
- Caches improve performance by storing recently accessed data from main memory closer to the processor, reducing access time compared to main memory. This can increase hit rates but requires managing cache misses and write policies.
This document discusses the memory hierarchy in computers. It begins by explaining that computer memory is organized in a pyramid structure from fastest and smallest memory (cache) to slower and larger auxiliary memory. The main types of memory discussed are RAM, ROM, cache memory, and auxiliary storage. RAM is further divided into SRAM and DRAM. The document provides details on the characteristics of each memory type including access speed, volatility, capacity and cost. Diagrams are included to illustrate concepts like RAM, ROM, cache levels and auxiliary devices. Virtual memory is also briefly introduced at the end.
The document discusses the concept of virtual memory. Virtual memory allows a program to access more memory than what is physically available in RAM by storing unused portions of the program on disk. When a program requests data that is not currently in RAM, it triggers a page fault that causes the needed page to be swapped from disk into RAM. This allows the illusion of more memory than physically available through swapping pages between RAM and disk as needed by the program during execution.
1) The document discusses different types of micro-operations including arithmetic, logic, shift, and register transfer micro-operations.
2) It provides examples of common arithmetic operations like addition, subtraction, increment, and decrement. It also describes logic operations like AND, OR, XOR, and complement.
3) Shift micro-operations include logical shifts, circular shifts, and arithmetic shifts which affect the serial input differently.
Basic Computer Organization and Design
.....................................................................
The basic computer design represents all of the major concepts in CPU design without overwhelming students with the complexity of a modern commercial CPU.
The document discusses the memory hierarchy in computers. It describes the different levels of memory from fastest to slowest as register memory, cache memory, main memory (RAM and ROM), and auxiliary memory (magnetic tapes, hard disks, etc.). The main memory directly communicates with the CPU while the auxiliary memory provides backup storage and needs to transfer data to main memory to be accessed by the CPU. A cache memory is also used to increase processing speed.
Control Units : Microprogrammed and Hardwired:control unitabdosaidgkv
The document discusses control units in CPUs. There are two main methods for implementing control units: hardwired and microprogrammed. A hardwired control unit generates control signals through circuitry using logic gates, while a microprogrammed control unit generates control signals by executing a stored microprogram. Overall, hardwired control units are faster but less flexible, while microprogrammed control units are slower but more flexible and modifiable.
The document discusses various aspects of I/O organization in a computer system. It describes the input-output interface that provides a method for transferring information between internal storage and external I/O devices. It discusses asynchronous data transfer techniques like strobe control and handshaking. It also covers asynchronous serial transmission, different modes of data transfer like programmed I/O, interrupt-initiated I/O, and direct memory access (DMA).
Associative memory, also known as content-addressable memory (CAM), allows data to be searched based on its content rather than its location. It consists of a memory array, argument register (containing the search word), key register (specifying which bits to compare), and match register (indicating matching locations). All comparisons are done in parallel. Associative memory provides faster searching than conventional memory but is more expensive due to the additional comparison circuitry in each cell. It is well-suited for applications requiring very fast searching such as databases and virtual memory address translation.
The document discusses different levels of computer memory organization. It describes the memory hierarchy from fastest to slowest as registers, cache memory, main memory, and auxiliary memory such as magnetic disks and tapes. It explains how each level of memory trades off speed versus cost and capacity. The document also covers virtual memory and how it allows programs to access large logical addresses while physical memory remains small.
COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and Architecture COA Computer Organisation and ArchitectureCOA Computer Organisation and Architecture
The document discusses cache memory, virtual memory, and memory management in hardware. It describes how cache memory stores frequently used data from main memory for faster CPU access. Virtual memory allows programs to access more memory than physically available by mapping virtual addresses to physical addresses. The performance of cache memory is measured by hit and miss rates, with hits accessing the cache faster and misses requiring additional time to retrieve data from main memory.
This document discusses different memory management strategies used in operating systems. It describes basic hardware components like main memory, registers, and cache. It then covers address binding techniques, logical vs physical address spaces, and dynamic loading and linking of processes. The rest of the document discusses paging as a memory management strategy, including hardware support through page tables, protection using valid-invalid bits, and sharing of pages between processes.
The document discusses different levels of computer memory and cache memory. It describes four levels of memory:
1) Register - Stores data accepted by the CPU.
2) Cache memory - Faster memory that temporarily stores frequently accessed data from main memory.
3) Main memory - The memory the computer currently works on but data is lost when powered off.
4) Secondary memory - External memory that stores data permanently but is slower than main memory.
It then discusses cache memory in more detail, describing it as very high-speed memory that stores copies of frequently used data from main memory to reduce average access time. It explains the concepts of cache hits, misses, and hit ratio. Finally, it
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
This document discusses different memory management techniques including:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation. Paging and segmentation address this by allowing non-contiguous allocation.
2. Paging maps logical addresses to physical frames through a page table. It supports non-contiguous allocation but has translation overhead that is reduced using translation lookaside buffers.
3. Segmentation divides memory into logical segments and uses a segment table to map logical to physical addresses. It matches the user's view of memory but external fragmentation remained an issue until combined with paging.
The document discusses the memory hierarchy in computers including main memory, cache memory, and auxiliary memory. It describes the different types of memory in terms of speed and cost, with cache memory being the fastest and most expensive, and auxiliary memory being the slowest and cheapest. It also discusses memory mapping techniques including direct mapping, associative mapping, and set associative mapping that improve cache hit rates. Virtual memory management using paging to map virtual to physical addresses is also summarized.
The document discusses various memory management techniques used by operating systems including memory allocation, paging, segmentation, virtual memory and page replacement algorithms. It provides details on how operating systems manage processes in memory using techniques like memory mapping, context switching, swapping and fragmentation handling. Various address translation mechanisms like logical, physical and virtual addresses are also summarized along with common page replacement algorithms like FIFO, LRU, OPT and their working.
Cache memory improves processor performance by storing copies of frequently used data from main memory closer to the processor in cache memory. There are separate instruction and data caches. When the processor needs to access data, it first checks the relevant cache - if the data is present (a cache hit) access is faster, if not (a cache miss) the data must be fetched from main memory which takes longer. Cache performance is measured by hit and miss rates, with lower miss rates improving performance. Cache entries contain the cached data as well as address tags to match cache contents with memory locations.
This document discusses computer architecture and parallel processing. It describes vector processing which can perform operations on multiple data elements simultaneously using a single instruction. Vector processors are more efficient than scalar processors as they reduce overhead. Cache memory is also discussed as a fast memory located between the CPU and main memory that stores frequently used data. Different levels of cache memory and mapping techniques like direct mapping and set associative mapping are covered. Finally, the document outlines different types of parallelism including bit-level, instruction-level, task-level, and data-level parallelism.
Cache memory is a memory located close to the processor that stores frequently accessed data. There are three main types of cache mapping: direct mapped, set associative, and fully associative. A cache hit occurs when requested data is in cache, while a cache miss requires accessing slower main memory. Virtual memory uses main memory as a cache for secondary storage through address translation. Translation lookaside buffers cache recent virtual to physical address translations to improve performance. Interrupts allow I/O devices to signal the processor asynchronously, with interrupt service routines executing in response.
The document discusses different memory management techniques used in operating systems:
1. Programs go through several steps before execution - compilation, loading, and execution where address binding can occur.
2. Memory management schemes separate logical and physical addresses using techniques like paging and segmentation to map virtual to physical addresses.
3. Swapping allows processes to be temporarily moved out of memory to disk to improve memory utilization at the cost of performance.
The document discusses memory management techniques used in computer systems, including memory partitioning, paging, segmentation, and virtual memory. It provides details on:
1) How memory is divided between the operating system and currently running program.
2) The use of fixed and variable size partitions and their tradeoffs.
3) How paging divides programs and memory into pages to more efficiently allocate memory.
4) How segmentation further subdivides memory to simplify programming and enable access controls.
5) How virtual memory uses paging, disk storage, and demand paging to make programs appear larger than physical memory.
The document discusses different memory management techniques used in operating systems. It begins with an overview of processes entering memory from an input queue. It then covers binding of instructions and data to memory at compile time, load time, or execution time. Key concepts discussed include logical vs physical addresses, the memory management unit (MMU), dynamic loading and linking, overlays, swapping, contiguous allocation, paging using page tables and frames, and fragmentation. Hierarchical paging, hashed page tables, and inverted page tables are also summarized.
The document discusses several memory management techniques including paging, segmentation, and swapping. Paging divides memory into fixed-size blocks called frames and logical memory into blocks called pages. It uses a page table to map logical to physical addresses. Segmentation divides programs into logical segments like code and data and allows segments to be placed anywhere in memory. Swapping temporarily moves processes out of memory to disk to allow other processes to run.
This document discusses various computer arithmetic operations including addition, subtraction, multiplication, and division for signed magnitude and two's complement data representations. It describes the Booth multiplication algorithm, array multipliers for performing multiplication using combinational circuits, and the division algorithm. It also covers detecting divide overflow conditions.
The document provides an introduction to computer security including:
- The basic components of security such as confidentiality, integrity, and availability.
- Common security threats like snooping, modification, and denial of service attacks.
- Issues with security including operational challenges and human factors.
- An overview of security policies, access control models, and security models like Bell-LaPadula and Biba.
Cookies and sessions allow servers to remember information about users across multiple web pages. Cookies are small files stored on a user's computer that identify users and can store data to be accessed on subsequent page requests. Sessions use cookies to identify users and store temporary data on the server side to be accessed across multiple pages in one application, such as usernames or preferences. Both cookies and sessions must be started before any page output to ensure headers are sent before the page body.
This document discusses different aspects of functions in programming including declaring and calling functions, passing arguments to functions, and returning values from functions. It also covers variable scope. Some key points covered are declaring functions with and without arguments, specifying default values, returning single values or arrays from functions, and understanding variable scope and how it relates to the global and $GLOBALS keywords and array.
This document discusses various aspects of working with web forms in PHP, including:
1) Useful server variables for forms like QUERY_STRING and SERVER_NAME.
2) Accessing form parameters submitted to the server.
3) Processing forms with functions, including validating form data with techniques like checking for required fields and valid email addresses.
4) Displaying default values or error messages for form fields.
5) Stripping HTML tags from form inputs and encoding special characters for safe display.
The document provides examples of implementing each of these techniques.
The document discusses various programming concepts related to decision making and repetition in code including understanding true and false values, using if/elseif/else statements, equality and relational operators, logical operators, and using while and for loops to repeat code. Specific topics covered include evaluating booleans, making single and multi-line if statements, comparing different data types, negation, and printing select menus with loops.
This document discusses working with arrays in PHP. It covers array basics like creating and accessing arrays, looping through arrays with foreach and for loops, modifying arrays by adding/removing elements and sorting arrays. It also discusses multidimensional arrays, how to create them and access elements within them.
This document discusses text and numbers in programming. It covers defining and manipulating text strings using single or double quotes. Escape characters can be used inside strings. Text can be validated and formatted using various string functions like trim(), strlen(), strtoupper(), substr(), and str_replace(). Numbers can be integers or floats. Variables hold data and can be operated on with arithmetic and assignment operators like +, -, *, /, %, and .=. Variables can also be incremented, decremented, and placed inside strings.
This document provides an introduction and overview of PHP for beginners. It discusses PHP's use for building websites, how PHP code is run on web servers and accessed through browsers. It then highlights some key advantages of PHP like being free, cross-platform, and widely used. It demonstrates a basic "Hello World" PHP program and shows how to output HTML forms and formatted numbers. Finally, it outlines some basic rules of PHP programs regarding tags, syntax, whitespace, comments, and case sensitivity.
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2. Memory Hierarchy
Memory unit is essential component of digital
computer since it is needed for storing programs and
data.
Memory unit that communicates directly with CPU is
called Main memory.
Devices that provide backup storage is called
auxiliary memory.
Only programs and data currently needed by
processor reside in the main memory.
All other information is stored in auxiliary memory
and transferred to main memory when needed.
3.
4.
5. Memory hierarchy system consist of all storage
devices from auxiliary memory to main memory to
cache memory
As one goes down the hierarchy :
Cost per bit decreases.
Capacity increases.
Access time increases.
Frequency of access by the processor decreases.
6. Main Memory
It is the memory used to store programs and data
during the computer operation.
The principal technology is based on semiconductor
integrated circuits.
It consists of RAM and ROM chips.
RAM chips are available in two form static and
dynamic.
7. SRAM DRAM
Uses capacitor for storing
information
Uses Flip flop
More cells per unit area due
to smaller cell size.
Needs more space for same
capacity
Cheap and smaller in size Expensive and bigger in size
Slower and analog device Faster and digital device
Requires refresh circuit No need
Used in main memory Used in cache
8. ROM is uses random access method.
It is used for storing programs that are permanent
and the tables of constants that do not change.
ROM store program called bootstrap loader whose
function is to start the computer software when the
power is turned on.
When the power is turned on, the hardware of the
computer sets the program counter to the first
address of the bootstrap loader.
9.
10.
11. For the same size chip it is possible to have more bits
of ROM than of RAM, because the internal binary
cells in ROM occupy less space than in RAM,
For this reason the diagram specifies 512 byte ROM
and 128 bytes RAM.
12. Memory address Map
Designer must specify the size and the type(RAM or
ROM) of memory to be used for particular
application.
The addressing of the memory is then established by
means of table called memory address map that
specifies the memory address assign to each chip.
Let us consider an example in which computer needs
512 bytes of RAM and ROM as well and we have to
use the chips of size 128 bytes for RAM and 512 bytes
for ROM.
13.
14.
15. Associative Memory
To search particular data in memory, data is read
from certain address and compared if the match is
not found content of the next address is accessed and
compared.
This goes on until required data is found. The
number of access depend on the location of data and
efficiency of searching algorithm.
The searching time can be reduced if data is searched
on the basis of content.
16. A memory unit accessed by content is called
associative memory or content addressable
memory(CAM)
This type of memory is accessed simultaneously and
in parallel on the basis of data content.
Memory is capable of finding empty unused location
to store the word.
These are used in the application where search time
is very critical and must be very short.
17.
18. It consists memory array of m words with n bits per
words
Argument register A and key register K have n bits
one for each bit of word.
Match register has m bits, one for each memory
word.
Each word in memory is compared in parallel with
the content of the A register. For the word that
match corresponding bit in the match register is set.
19. Key register provide the mask for choosing the
particular field in A register.
The entire content of A register is compared if key
register content all 1.
Otherwise only bit that have 1 in key register are
compared.
If the compared data is matched corresponding bits
in the match register are set.
Reading is accomplished by sequential access in
memory for those words whose bit are set.
22. Match Logic
Let us neglect the key register and compare the
content of argument register with memory content.
Word i is equal to argument in A if Aj=Fij for
j=1,2,3,4……..n
The equality of two bits is expressed as
xj =1 if bits are equal and 0 otherwise.
23.
24. Let us include key register. If Kj=0 then there is no
need to compare Aj and Fij.
Only when Kj=1, comparison is needed.
This achieved by ORing each term with Kj.
25.
26. Read Operation
If more than one word match with the content, all
the matched words will have 1 in the corresponding
bit position in match register.
Matched words are then read in sequence by
applying a read signal to each word line.
In most application, the associative memory stores a
table with no two identical items under a given key.
27. Write Operation
If the entire memory is loaded with new information
at once prior to search operation then writing can be
done by addressing each location in sequence.
Tag register contain as many bits as there are words
in memory.
It contain 1 for active word and 0 for inactive word.
If the word is to be inserted, tag register is scanned
until 0 is found and word is written at that position
and bit is change to 1.
28. Cache Memory
Analysis of large number of program shows that
reference to memory at any given interval of time
tend to be confined to few localized area in memory.
This is known as locality of reference.
If the active portion of program and data are placed
in fast memory, then average execution time of the
program can be reduced. Such fast memory is called
cache memory.
It is placed in between the main memory and the
CPU.
29.
30. When the CPU need to access the memory it first
search in cache. If word is found, it is read.
If the word is not found, it is read from main
memory and a block of data is transferred from main
memory to cache which contain the current word.
If the word is found in cache, it is said hit. If the
word is not found, it is called miss.
Performance of cache is measured in terms of hit
ratio which ratio of total hit to total memory access
by CPU.
31. Mapping Techniques
The transformation of data from main memory to
cache is known as mapping process. Three types of
mapping procedures are:
Associative Mapping
Direct Mapping
Set-Associative Mapping
32. Associative Mapping
Fastest and most flexible cache organization uses
associative memory.
It stores both address and content of memory word.
Address is placed in argument register and memory
is searched for matching address.
If address is found corresponding data is read.
If address is not found, it is read from main memory
and transferred to cache.
33. If the cache is full, an address- word pair must be
displaced.
Various algorithm are used to determine which pair
to displace. Some of them are FIFO(First In First
Out), LRU(Least Recently Used) etc.
34. Direct Memory
CPU address is divided into two fields tag and index.
Index field is required to access cache memory and
total address is used to access main memory.
If there are 2^k words in cache and 2^n words in
main memory, then n bit memory address is divided
into two parts. k bits for index field and n-k bits for
tag field.
37. When CPU generates memory request, index field is
used to access the cache.
Tag field of the CPU address is compared with the
tag in the word read. If the tag match, there is hit.
If the tag does not match, word is read from main
memory and updated in cache.
This example use the block size of 1.
The same organization can be implemented for block
size 8.
38. The index field is divided into two parts: block field
and word field.
In 512 word cache there are 64 blocks of 8 words
each(64*8=512).
Block is specified with 6 bit field and word within
block with 3 bit field.
Every time miss occur, entire block of 8 word is
transferred from main memory to cahche.
39.
40. Set-Associative Mapping
In direct mapping two words with same index in
their address but different tag values can’t reside
simultaneously in memory.
In this mapping, each data word is stored together
with its tag and number of tag-data items in one
word of the cache is said to form set.
In general, a set associative cache of set size k will
accommodate k words of main memory in each word
of cache.
41.
42. When a miss occur and the set is full, one of the tag
data item is replaced with new value using various
algorithm.
43. Writing into Cache
Writing into cache can be done in two ways:
Write through
Write Back
In write through, whenever write operation is
performed in cache memory, main memory is also
updated in parallel with the cache.
In write back, only cache is updated and marked by
the flag. When the word is removed from cache, flag
is checked if it is set the corresponding address in
main memory is updated.
44. Cache Initialization
When power is turned on, cache contain invalid data
indicated by valid bit value 0.
Valid bit of word is set whenever the word is read
from main memory and updated in cache.
If valid bit is 0, new word automatically replace the
invalid data.
45. Virtual Memory
Virtual memory is a concept used in computer that
permit the user to construct a program as though
large memory space is available equal to auxiliary
memory.
It give the illusion that computer has large memory
even though computer has relatively small main
memory.
It has mechanism that convert generated address
into correct main memory address.
46. Address Space and Memory Space
An address used by the programmer is called virtual
address and set of such address is called address
space.
An address in main memory is called physical
address. The set of such location is called memory
space.
47.
48.
49. Address Mapping Using Pages
The main memory is broken down into groups of
equal size called blocks.
Term pages refers to groups of address space of same
size.
Although page and block are of equal size, page refer
to organization of address space and block represent
the organization of memory space.
The term page frame is sometimes used to denote
block.
50.
51.
52.
53. Page Replacement
The program is executed from main memory until
page required is not available.
If page is not available, this condition is called page
fault. When it occurs, present program is suspended
until the page required is brought into main
memory.
If main memory is full, pages to remove is
determined from the replacement algorithm used.