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Computer Arithmetic

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Kamal Acharya

This document discusses various computer arithmetic operations including addition, subtraction, multiplication, and division for signed magnitude and two's complement data representations. It describes the Booth multiplication algorithm, array multipliers for performing multiplication using combinational circuits, and the division algorithm. It also covers detecting divide overflow conditions.

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๏ƒ˜Addition and subtraction of Signed Magnitude Data ๏ƒ˜Addition and subtraction of Signed 2โ€™s Complement Data ๏ƒ˜Multiplication of Signed Magnitude Data ๏ƒ˜Booth Multiplication Algorithm ๏ƒ˜Division Algorithm Computer Arithmetic
Signed Magnitude Multiplication
Signed 2โ€™s Complement Multiplication
Array Multiplier ๏‚— Checking the bit of multiplier adding and then shifting is sequential operation. ๏‚— Multiplication can also be done with the help of combinational circuits in which whole operation can be performed in one cycle. ๏‚— This circuit is the array multiplier.
๏‚— For j multiplier bits and k multiplicand bits we need j*k AND gates and (j-1) k bits adder to produce a product of j+k bits.
Division Algorithm ๏‚— The hardware required for this is same as that of the multiplication of signed magnitude data. ๏‚— Sign and magnitude of the divisor and dividend are treated separately. ๏‚— Example shows the division of 0111000000 by 10001 here in both case only magnitude bits are used.
Divide Overflow ๏‚— Dividend is twice bit long then divisor. ๏‚— The condition of overflow can be detected when the upper half of the dividend is greater or equal to the divisor. ๏‚— Another problem is division by 0. ๏‚— In case of overflow DVF(divide overflow flag) is used to indicate the condition.
Computer Arithmetic
Computer Arithmetic

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Computer Arithmetic

  • 1. ๏ƒ˜Addition and subtraction of Signed Magnitude Data ๏ƒ˜Addition and subtraction of Signed 2โ€™s Complement Data ๏ƒ˜Multiplication of Signed Magnitude Data ๏ƒ˜Booth Multiplication Algorithm ๏ƒ˜Division Algorithm Computer Arithmetic
  • 2.
  • 3.
  • 4.
  • 5.
  • 6.
  • 8.
  • 9.
  • 10. Signed 2โ€™s Complement Multiplication
  • 11.
  • 12.
  • 13. Array Multiplier ๏‚— Checking the bit of multiplier adding and then shifting is sequential operation. ๏‚— Multiplication can also be done with the help of combinational circuits in which whole operation can be performed in one cycle. ๏‚— This circuit is the array multiplier.
  • 14.
  • 15.
  • 16. ๏‚— For j multiplier bits and k multiplicand bits we need j*k AND gates and (j-1) k bits adder to produce a product of j+k bits.
  • 17. Division Algorithm ๏‚— The hardware required for this is same as that of the multiplication of signed magnitude data. ๏‚— Sign and magnitude of the divisor and dividend are treated separately. ๏‚— Example shows the division of 0111000000 by 10001 here in both case only magnitude bits are used.
  • 18.
  • 19. Divide Overflow ๏‚— Dividend is twice bit long then divisor. ๏‚— The condition of overflow can be detected when the upper half of the dividend is greater or equal to the divisor. ๏‚— Another problem is division by 0. ๏‚— In case of overflow DVF(divide overflow flag) is used to indicate the condition.
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