尊敬的 微信汇率：1円 ≈ 0.046166 元 支付宝汇率：1円 ≈ 0.046257元 [退出登录]
SlideShare a Scribd company logo

Cache memory

•Download as PPS, PDF•
•
Anuj Modi
Anuj Modi

Cache memory is a small, fast memory located between the CPU and main memory. It stores copies of frequently used instructions and data to accelerate access and improve performance. There are different mapping techniques for cache including direct mapping, associative mapping, and set associative mapping. When the cache is full, replacement algorithms like LRU and FIFO are used to determine which content to remove. The cache can write to main memory using either a write-through or write-back policy.

1 of 18
CACHE MEMORY Maninder Kaur professormaninder@gmail.com 1 www.eazynotes.com 24-Nov-2010
What is Cache Memory? Cache memory is a small, high-speed RAM buffer located between the CPU and main memory. Cache memory holds a copy of the instructions (instruction cache) or data (operand or data cache) currently being used by the CPU. The main purpose of a cache is to accelerate your computer while keeping the price of the computer low. 2 www.eazynotes.com 24-Nov-2010
Placement of Cache in computer 3 www.eazynotes.com 24-Nov-2010
Hit Ratio The ratio of the total number of hits divided by the total CPU accesses to memory (i.e. hits plus misses) is called Hit Ratio. Hit Ratio = Total Number of Hits / (Total Number of Hits + Total Number of Miss) 4 www.eazynotes.com 24-Nov-2010
Example A system with 512 x 12 cache and 32 K x 12 of main memory. 5 www.eazynotes.com 24-Nov-2010
Types of Cache Mapping 1. Direct Mapping 2. Associative Mapping 3. Set Associative Mapping 6 www.eazynotes.com 24-Nov-2010
1. Direct Mapping  The direct mapping technique is simple and inexpensive to implement.  When the CPU wants to access data from memory, it places a address. The index field of CPU address is used to access address.  The tag field of CPU address is compared with the associated tag in the word read from the cache.  If the tag-bits of CPU address is matched with the tag-bits of cache, then there is a hit and the required data word is read from cache.  If there is no match, then there is a miss and the required data word is stored in main memory. It is then transferred from main memory to cache memory with the new tag. 7 www.eazynotes.com 24-Nov-2010
1. Direct Mapping 8 www.eazynotes.com 24-Nov-2010
1. Direct Mapping 9 www.eazynotes.com 24-Nov-2010
2. Associative Mapping An associative mapping uses an associative memory. This memory is being accessed using its contents. Each line of cache memory will accommodate the address (main memory) and the contents of that address from the main memory. That is why this memory is also called Content Addressable Memory (CAM). It allows each block of main memory to be stored in the cache. 10 www.eazynotes.com 24-Nov-2010
2. Associative Mapping 11 www.eazynotes.com 24-Nov-2010
3. Set Associative Mapping That is the easy control of the direct mapping cache and the more flexible mapping of the fully associative cache.  In set associative mapping, each cache location can have more than one pair of tag + data items. That is more than one pair of tag and data are residing at the same location of cache memory. If one cache location is holding two pair of tag + data items, that is called 2-way set associative mapping. 12 www.eazynotes.com 24-Nov-2010
3. Two-Way Set Associative Mapping 13 www.eazynotes.com 24-Nov-2010
Replacement Algorithms of Cache Memory  Replacement algorithms are used when there are no available space in a cache in which to place a data. Four of the most common cache replacement algorithms are described below:  Least Recently Used (LRU):  The LRU algorithm selects for replacement the item that has been least recently used by the CPU.  First-In-First-Out (FIFO):  The FIFO algorithm selects for replacement the item that has been in the cache from the longest time.  Least Frequently Used (LRU):  The LRU algorithm selects for replacement the item that has been least frequently used by the CPU.  Random:  The random algorithm selects for replacement the item randomly. 14 www.eazynotes.com 24-Nov-2010
Writing into Cache When memory write operations are performed, CPU first writes into the cache memory. These modifications made by CPU during a write operations, on the data saved in cache, need to be written back to main memory or to auxiliary memory. These two popular cache write policies (schemes) are: Write-Through Write-Back 15 www.eazynotes.com 24-Nov-2010
Write-Through In a write through cache, the main memory is updated each time the CPU writes into cache. The advantage of the write-through cache is that the main memory always contains the same data as the cache contains. This characteristic is desirable in a system which uses direct memory access scheme of data transfer. The I/O devices communicating through DMA receive the most recent data. 16 www.eazynotes.com 24-Nov-2010
Write-Back In a write back scheme, only the cache memory is updated during a write operation. The updated locations in the cache memory are marked by a flag so that later on, when the word is removed from the cache, it is copied into the main memory. The words are removed from the cache time to time to make room for a new block of words. 17 www.eazynotes.com 24-Nov-2010
18 Jan 26, 2013 www.eazynotes.com

Recommended

Cache memory
Cache memoryCache memory
Cache memory
Ansari Maviya
 
Memory organization in computer architecture
Memory organization in computer architectureMemory organization in computer architecture
Memory organization in computer architecture
Faisal Hussain
 
Direct memory access (dma)
Direct memory access (dma)Direct memory access (dma)
Direct memory access (dma)
Zubair Khalid
 
Memory Hierarchy
Memory HierarchyMemory Hierarchy
Memory Hierarchy
chauhankapil
 
Virtual memory
Virtual memoryVirtual memory
Virtual memory
Anuj Modi
 
Asynchronous data transfer
Asynchronous data transferAsynchronous data transfer
Asynchronous data transfer
priya Nithya
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
Kamal Acharya
 
Cache memory
Cache memoryCache memory
Cache memory
Shailesh Tanwar
 

Recommended

Cache memory
Cache memoryCache memory
Cache memory
Ansari Maviya
 
Memory organization in computer architecture
Memory organization in computer architectureMemory organization in computer architecture
Memory organization in computer architecture
Faisal Hussain
 
Direct memory access (dma)
Direct memory access (dma)Direct memory access (dma)
Direct memory access (dma)
Zubair Khalid
 
Memory Hierarchy
Memory HierarchyMemory Hierarchy
Memory Hierarchy
chauhankapil
 
Virtual memory
Virtual memoryVirtual memory
Virtual memory
Anuj Modi
 
Asynchronous data transfer
Asynchronous data transferAsynchronous data transfer
Asynchronous data transfer
priya Nithya
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
Kamal Acharya
 
Cache memory
Cache memoryCache memory
Cache memory
Shailesh Tanwar
 
Memory organization (Computer architecture)
Memory organization (Computer architecture)Memory organization (Computer architecture)
Memory organization (Computer architecture)
Sandesh Jonchhe
 
Memory management
Memory managementMemory management
Memory management
Muhammad Fayyaz
 
Input Output Organization
Input Output OrganizationInput Output Organization
Input Output Organization
Kamal Acharya
 
Cache Memory
Cache Memory Cache Memory
Cache Memory
sathish sak
 
Direct memory access
Direct memory accessDirect memory access
Direct memory access
shubham kuwar
 
Modes of transfer
Modes of transferModes of transfer
Modes of transfer
Andhra University
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memory
Mazin Alwaaly
 
Cache memory ppt
Cache memory ppt Cache memory ppt
Cache memory ppt
Arpita Naik
 
Direct Memory Access(DMA)
Direct Memory Access(DMA)Direct Memory Access(DMA)
Direct Memory Access(DMA)
Page Maker
 
Virtual memory ppt
Virtual memory pptVirtual memory ppt
Virtual memory ppt
Punjab College Of Technical Education
 
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)
Gaditek
 
Modes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output OrganizationModes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output Organization
MOHIT AGARWAL
 
bus and memory tranfer (computer organaization)
bus and memory tranfer (computer organaization)bus and memory tranfer (computer organaization)
bus and memory tranfer (computer organaization)
Siddhi Viradiya
 
Part I:Introduction to assembly language
Part I:Introduction to assembly languagePart I:Introduction to assembly language
Part I:Introduction to assembly language
Ahmed M. Abed
 
Computer architecture input output organization
Computer architecture input output organizationComputer architecture input output organization
Computer architecture input output organization
Mazin Alwaaly
 
Computer organization memory
Computer organization memoryComputer organization memory
Computer organization memory
Deepak John
 
Micro program example
Micro program exampleMicro program example
Micro program example
rajshreemuthiah
 
Memory mapping
Memory mappingMemory mapping
Memory mapping
SnehalataAgasti
 
memory hierarchy
memory hierarchymemory hierarchy
memory hierarchy
sreelakshmikv
 
Assembly language
Assembly languageAssembly language
Assembly language
shashank puthran
 
Cpu caching concepts mr mahesh
Cpu caching concepts mr maheshCpu caching concepts mr mahesh
Cpu caching concepts mr mahesh
Faridabad
 
IS 139 Lecture 7
IS 139 Lecture 7IS 139 Lecture 7
IS 139 Lecture 7
wajanga
 

More Related Content

What's hot

Memory organization (Computer architecture)
Memory organization (Computer architecture)Memory organization (Computer architecture)
Memory organization (Computer architecture)
Sandesh Jonchhe
 
Memory management
Memory managementMemory management
Memory management
Muhammad Fayyaz
 
Input Output Organization
Input Output OrganizationInput Output Organization
Input Output Organization
Kamal Acharya
 
Cache Memory
Cache Memory Cache Memory
Cache Memory
sathish sak
 
Direct memory access
Direct memory accessDirect memory access
Direct memory access
shubham kuwar
 
Modes of transfer
Modes of transferModes of transfer
Modes of transfer
Andhra University
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memory
Mazin Alwaaly
 
Cache memory ppt
Cache memory ppt Cache memory ppt
Cache memory ppt
Arpita Naik
 
Direct Memory Access(DMA)
Direct Memory Access(DMA)Direct Memory Access(DMA)
Direct Memory Access(DMA)
Page Maker
 
Virtual memory ppt
Virtual memory pptVirtual memory ppt
Virtual memory ppt
Punjab College Of Technical Education
 
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)
Gaditek
 
Modes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output OrganizationModes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output Organization
MOHIT AGARWAL
 
bus and memory tranfer (computer organaization)
bus and memory tranfer (computer organaization)bus and memory tranfer (computer organaization)
bus and memory tranfer (computer organaization)
Siddhi Viradiya
 
Part I:Introduction to assembly language
Part I:Introduction to assembly languagePart I:Introduction to assembly language
Part I:Introduction to assembly language
Ahmed M. Abed
 
Computer architecture input output organization
Computer architecture input output organizationComputer architecture input output organization
Computer architecture input output organization
Mazin Alwaaly
 
Computer organization memory
Computer organization memoryComputer organization memory
Computer organization memory
Deepak John
 
Micro program example
Micro program exampleMicro program example
Micro program example
rajshreemuthiah
 
Memory mapping
Memory mappingMemory mapping
Memory mapping
SnehalataAgasti
 
memory hierarchy
memory hierarchymemory hierarchy
memory hierarchy
sreelakshmikv
 
Assembly language
Assembly languageAssembly language
Assembly language
shashank puthran
 

What's hot (20)

Memory organization (Computer architecture)
Memory organization (Computer architecture)Memory organization (Computer architecture)
Memory organization (Computer architecture)
 
Memory management
Memory managementMemory management
Memory management
 
Input Output Organization
Input Output OrganizationInput Output Organization
Input Output Organization
 
Cache Memory
Cache Memory Cache Memory
Cache Memory
 
Direct memory access
Direct memory accessDirect memory access
Direct memory access
 
Modes of transfer
Modes of transferModes of transfer
Modes of transfer
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memory
 
Cache memory ppt
Cache memory ppt Cache memory ppt
Cache memory ppt
 
Direct Memory Access(DMA)
Direct Memory Access(DMA)Direct Memory Access(DMA)
Direct Memory Access(DMA)
 
Virtual memory ppt
Virtual memory pptVirtual memory ppt
Virtual memory ppt
 
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)
 
Modes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output OrganizationModes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output Organization
 
bus and memory tranfer (computer organaization)
bus and memory tranfer (computer organaization)bus and memory tranfer (computer organaization)
bus and memory tranfer (computer organaization)
 
Part I:Introduction to assembly language
Part I:Introduction to assembly languagePart I:Introduction to assembly language
Part I:Introduction to assembly language
 
Computer architecture input output organization
Computer architecture input output organizationComputer architecture input output organization
Computer architecture input output organization
 
Computer organization memory
Computer organization memoryComputer organization memory
Computer organization memory
 
Micro program example
Micro program exampleMicro program example
Micro program example
 
Memory mapping
Memory mappingMemory mapping
Memory mapping
 
memory hierarchy
memory hierarchymemory hierarchy
memory hierarchy
 
Assembly language
Assembly languageAssembly language
Assembly language
 

Similar to Cache memory

Cpu caching concepts mr mahesh
Cpu caching concepts mr maheshCpu caching concepts mr mahesh
Cpu caching concepts mr mahesh
Faridabad
 
IS 139 Lecture 7
IS 139 Lecture 7IS 139 Lecture 7
IS 139 Lecture 7
wajanga
 
CPU Caching Concepts
CPU Caching ConceptsCPU Caching Concepts
CPU Caching Concepts
Abhijit K Rao
 
Cache memoy designed by Mohd Tariq
Cache memoy designed by Mohd TariqCache memoy designed by Mohd Tariq
Cache memoy designed by Mohd Tariq
Mohd Tariq
 
lecture-2-3_Memory.pdf,describing memory
lecture-2-3_Memory.pdf,describing memorylecture-2-3_Memory.pdf,describing memory
lecture-2-3_Memory.pdf,describing memory
floraaluoch3
 
Cache memory
Cache memoryCache memory
Cache memory
Muhammad Imran
 
Cache memory
Cache memoryCache memory
Cache memory
Abir Rahman
 
Virtual Memory vs Cache Memory
Virtual Memory vs Cache MemoryVirtual Memory vs Cache Memory
Virtual Memory vs Cache Memory
Ashik Iqbal
 
Cache Memory.pptx
Cache Memory.pptxCache Memory.pptx
Cache Memory.pptx
ssusere16bd9
 
computer-memory
computer-memorycomputer-memory
computer-memory
Bablu Shofi
 
Memory organization.pptx
Memory organization.pptxMemory organization.pptx
Memory organization.pptx
RamanRay105
 
Cache Memory
Cache MemoryCache Memory
Cache Memory
Subid Biswas
 
cachememory-210517060741 (1).pdf
cachememory-210517060741 (1).pdfcachememory-210517060741 (1).pdf
cachememory-210517060741 (1).pdf
OmGadekar2
 
Memory_Unit Cache Main Virtual Associative
Memory_Unit Cache Main Virtual AssociativeMemory_Unit Cache Main Virtual Associative
Memory_Unit Cache Main Virtual Associative
RNShukla7
 
Cache memory
Cache memoryCache memory
Cache memory
Eklavya Gupta
 
Computer architecture
Computer architectureComputer architecture
Computer architecture
Perfectly Perfect
 
Unit 5-lecture-2
Unit 5-lecture-2Unit 5-lecture-2
Unit 5-lecture-2
vishal choudhary
 
Unit 6 cache coherence
Unit 6 cache coherenceUnit 6 cache coherence
Unit 6 cache coherence
Dipesh Vaya
 
Computer architecture cache memory
Computer architecture cache memoryComputer architecture cache memory
Computer architecture cache memory
Mazin Alwaaly
 
computerarchitecturecachememory-170927134432.pdf
computerarchitecturecachememory-170927134432.pdfcomputerarchitecturecachememory-170927134432.pdf
computerarchitecturecachememory-170927134432.pdf
ssuserf86fba
 

Similar to Cache memory (20)

Cpu caching concepts mr mahesh
Cpu caching concepts mr maheshCpu caching concepts mr mahesh
Cpu caching concepts mr mahesh
 
IS 139 Lecture 7
IS 139 Lecture 7IS 139 Lecture 7
IS 139 Lecture 7
 
CPU Caching Concepts
CPU Caching ConceptsCPU Caching Concepts
CPU Caching Concepts
 
Cache memoy designed by Mohd Tariq
Cache memoy designed by Mohd TariqCache memoy designed by Mohd Tariq
Cache memoy designed by Mohd Tariq
 
lecture-2-3_Memory.pdf,describing memory
lecture-2-3_Memory.pdf,describing memorylecture-2-3_Memory.pdf,describing memory
lecture-2-3_Memory.pdf,describing memory
 
Cache memory
Cache memoryCache memory
Cache memory
 
Cache memory
Cache memoryCache memory
Cache memory
 
Virtual Memory vs Cache Memory
Virtual Memory vs Cache MemoryVirtual Memory vs Cache Memory
Virtual Memory vs Cache Memory
 
Cache Memory.pptx
Cache Memory.pptxCache Memory.pptx
Cache Memory.pptx
 
computer-memory
computer-memorycomputer-memory
computer-memory
 
Memory organization.pptx
Memory organization.pptxMemory organization.pptx
Memory organization.pptx
 
Cache Memory
Cache MemoryCache Memory
Cache Memory
 
cachememory-210517060741 (1).pdf
cachememory-210517060741 (1).pdfcachememory-210517060741 (1).pdf
cachememory-210517060741 (1).pdf
 
Memory_Unit Cache Main Virtual Associative
Memory_Unit Cache Main Virtual AssociativeMemory_Unit Cache Main Virtual Associative
Memory_Unit Cache Main Virtual Associative
 
Cache memory
Cache memoryCache memory
Cache memory
 
Computer architecture
Computer architectureComputer architecture
Computer architecture
 
Unit 5-lecture-2
Unit 5-lecture-2Unit 5-lecture-2
Unit 5-lecture-2
 
Unit 6 cache coherence
Unit 6 cache coherenceUnit 6 cache coherence
Unit 6 cache coherence
 
Computer architecture cache memory
Computer architecture cache memoryComputer architecture cache memory
Computer architecture cache memory
 
computerarchitecturecachememory-170927134432.pdf
computerarchitecturecachememory-170927134432.pdfcomputerarchitecturecachememory-170927134432.pdf
computerarchitecturecachememory-170927134432.pdf
 

More from Anuj Modi

Android Technology
Android TechnologyAndroid Technology
Android Technology
Anuj Modi
 
Timing and-control-unit
Timing and-control-unitTiming and-control-unit
Timing and-control-unit
Anuj Modi
 
Synchronous and-asynchronous-data-transfer
Synchronous and-asynchronous-data-transferSynchronous and-asynchronous-data-transfer
Synchronous and-asynchronous-data-transfer
Anuj Modi
 
Registers and-common-bus
Registers and-common-busRegisters and-common-bus
Registers and-common-bus
Anuj Modi
 
Ram and-rom-chips
Ram and-rom-chipsRam and-rom-chips
Ram and-rom-chips
Anuj Modi
 
Memory
MemoryMemory
Memory
Anuj Modi
 
Computer instructions
Computer instructionsComputer instructions
Computer instructions
Anuj Modi
 
HTML Lesson 5-insert-and-align-graphics
HTML Lesson 5-insert-and-align-graphicsHTML Lesson 5-insert-and-align-graphics
HTML Lesson 5-insert-and-align-graphics
Anuj Modi
 
HTML Lesson 2-format-pages-and-text
HTML Lesson 2-format-pages-and-textHTML Lesson 2-format-pages-and-text
HTML Lesson 2-format-pages-and-textAnuj Modi
 
HTML Lesson 1-create-a-home-page
HTML Lesson 1-create-a-home-pageHTML Lesson 1-create-a-home-page
HTML Lesson 1-create-a-home-page
Anuj Modi
 
Introduction to-dbms
Introduction to-dbmsIntroduction to-dbms
Introduction to-dbms
Anuj Modi
 
DBA
DBADBA
DBA
Anuj Modi
 
Data models
Data modelsData models
Data models
Anuj Modi
 
Architecture of-dbms-and-data-independence
Architecture of-dbms-and-data-independenceArchitecture of-dbms-and-data-independence
Architecture of-dbms-and-data-independence
Anuj Modi
 
Central Processing Unit User View
Central Processing Unit User ViewCentral Processing Unit User View
Central Processing Unit User View
Anuj Modi
 
Microprogram Control
Microprogram Control Microprogram Control
Microprogram Control
Anuj Modi
 
Graphs In Data Structure
Graphs In Data StructureGraphs In Data Structure
Graphs In Data Structure
Anuj Modi
 
Graphs In Data Structure
Graphs In Data StructureGraphs In Data Structure
Graphs In Data Structure
Anuj Modi
 
B trees in Data Structure
B trees in Data StructureB trees in Data Structure
B trees in Data Structure
Anuj Modi
 

More from Anuj Modi (19)

Android Technology
Android TechnologyAndroid Technology
Android Technology
 
Timing and-control-unit
Timing and-control-unitTiming and-control-unit
Timing and-control-unit
 
Synchronous and-asynchronous-data-transfer
Synchronous and-asynchronous-data-transferSynchronous and-asynchronous-data-transfer
Synchronous and-asynchronous-data-transfer
 
Registers and-common-bus
Registers and-common-busRegisters and-common-bus
Registers and-common-bus
 
Ram and-rom-chips
Ram and-rom-chipsRam and-rom-chips
Ram and-rom-chips
 
Memory
MemoryMemory
Memory
 
Computer instructions
Computer instructionsComputer instructions
Computer instructions
 
HTML Lesson 5-insert-and-align-graphics
HTML Lesson 5-insert-and-align-graphicsHTML Lesson 5-insert-and-align-graphics
HTML Lesson 5-insert-and-align-graphics
 
HTML Lesson 2-format-pages-and-text
HTML Lesson 2-format-pages-and-textHTML Lesson 2-format-pages-and-text
HTML Lesson 2-format-pages-and-text
 
HTML Lesson 1-create-a-home-page
HTML Lesson 1-create-a-home-pageHTML Lesson 1-create-a-home-page
HTML Lesson 1-create-a-home-page
 
Introduction to-dbms
Introduction to-dbmsIntroduction to-dbms
Introduction to-dbms
 
DBA
DBADBA
DBA
 
Data models
Data modelsData models
Data models
 
Architecture of-dbms-and-data-independence
Architecture of-dbms-and-data-independenceArchitecture of-dbms-and-data-independence
Architecture of-dbms-and-data-independence
 
Central Processing Unit User View
Central Processing Unit User ViewCentral Processing Unit User View
Central Processing Unit User View
 
Microprogram Control
Microprogram Control Microprogram Control
Microprogram Control
 
Graphs In Data Structure
Graphs In Data StructureGraphs In Data Structure
Graphs In Data Structure
 
Graphs In Data Structure
Graphs In Data StructureGraphs In Data Structure
Graphs In Data Structure
 
B trees in Data Structure
B trees in Data StructureB trees in Data Structure
B trees in Data Structure
 

Cache memory

  • 1. CACHE MEMORY Maninder Kaur professormaninder@gmail.com 1 www.eazynotes.com 24-Nov-2010
  • 2. What is Cache Memory? Cache memory is a small, high-speed RAM buffer located between the CPU and main memory. Cache memory holds a copy of the instructions (instruction cache) or data (operand or data cache) currently being used by the CPU. The main purpose of a cache is to accelerate your computer while keeping the price of the computer low. 2 www.eazynotes.com 24-Nov-2010
  • 3. Placement of Cache in computer 3 www.eazynotes.com 24-Nov-2010
  • 4. Hit Ratio The ratio of the total number of hits divided by the total CPU accesses to memory (i.e. hits plus misses) is called Hit Ratio. Hit Ratio = Total Number of Hits / (Total Number of Hits + Total Number of Miss) 4 www.eazynotes.com 24-Nov-2010
  • 5. Example A system with 512 x 12 cache and 32 K x 12 of main memory. 5 www.eazynotes.com 24-Nov-2010
  • 6. Types of Cache Mapping 1. Direct Mapping 2. Associative Mapping 3. Set Associative Mapping 6 www.eazynotes.com 24-Nov-2010
  • 7. 1. Direct Mapping  The direct mapping technique is simple and inexpensive to implement.  When the CPU wants to access data from memory, it places a address. The index field of CPU address is used to access address.  The tag field of CPU address is compared with the associated tag in the word read from the cache.  If the tag-bits of CPU address is matched with the tag-bits of cache, then there is a hit and the required data word is read from cache.  If there is no match, then there is a miss and the required data word is stored in main memory. It is then transferred from main memory to cache memory with the new tag. 7 www.eazynotes.com 24-Nov-2010
  • 8. 1. Direct Mapping 8 www.eazynotes.com 24-Nov-2010
  • 9. 1. Direct Mapping 9 www.eazynotes.com 24-Nov-2010
  • 10. 2. Associative Mapping An associative mapping uses an associative memory. This memory is being accessed using its contents. Each line of cache memory will accommodate the address (main memory) and the contents of that address from the main memory. That is why this memory is also called Content Addressable Memory (CAM). It allows each block of main memory to be stored in the cache. 10 www.eazynotes.com 24-Nov-2010
  • 11. 2. Associative Mapping 11 www.eazynotes.com 24-Nov-2010
  • 12. 3. Set Associative Mapping That is the easy control of the direct mapping cache and the more flexible mapping of the fully associative cache.  In set associative mapping, each cache location can have more than one pair of tag + data items. That is more than one pair of tag and data are residing at the same location of cache memory. If one cache location is holding two pair of tag + data items, that is called 2-way set associative mapping. 12 www.eazynotes.com 24-Nov-2010
  • 13. 3. Two-Way Set Associative Mapping 13 www.eazynotes.com 24-Nov-2010
  • 14. Replacement Algorithms of Cache Memory  Replacement algorithms are used when there are no available space in a cache in which to place a data. Four of the most common cache replacement algorithms are described below:  Least Recently Used (LRU):  The LRU algorithm selects for replacement the item that has been least recently used by the CPU.  First-In-First-Out (FIFO):  The FIFO algorithm selects for replacement the item that has been in the cache from the longest time.  Least Frequently Used (LRU):  The LRU algorithm selects for replacement the item that has been least frequently used by the CPU.  Random:  The random algorithm selects for replacement the item randomly. 14 www.eazynotes.com 24-Nov-2010
  • 15. Writing into Cache When memory write operations are performed, CPU first writes into the cache memory. These modifications made by CPU during a write operations, on the data saved in cache, need to be written back to main memory or to auxiliary memory. These two popular cache write policies (schemes) are: Write-Through Write-Back 15 www.eazynotes.com 24-Nov-2010
  • 16. Write-Through In a write through cache, the main memory is updated each time the CPU writes into cache. The advantage of the write-through cache is that the main memory always contains the same data as the cache contains. This characteristic is desirable in a system which uses direct memory access scheme of data transfer. The I/O devices communicating through DMA receive the most recent data. 16 www.eazynotes.com 24-Nov-2010
  • 17. Write-Back In a write back scheme, only the cache memory is updated during a write operation. The updated locations in the cache memory are marked by a flag so that later on, when the word is removed from the cache, it is copied into the main memory. The words are removed from the cache time to time to make room for a new block of words. 17 www.eazynotes.com 24-Nov-2010
  • 18. 18 Jan 26, 2013 www.eazynotes.com
  翻译：