Data transferschemes

Prepared by
Ankush Srivastava
anksri000@gmail.com

 A wide variety of IO devices having wide range
of speed and other different characteristics are
available .A slow responding IO device cannot
transfer data when microprocessor issues
instruction for it as it takes some time to get
ready.
 Transfers rates of peripherals is usually slower
than the transfer rates of CPU.
 Operating modes of peripheral are different
from each other and each must be controlled
so as not to disturb the operation of each
other peripherals connected to CPU.

Different types of data transfer techniques are available
which can be broadly divided into two categories:-

 MICROPROCESSOR CONTROLLED :- HERE data
transfer is controlled by microprocessor.
Microprocessor is primarily responsible for data transfer
whether from I/o to the CPU or to the memory or vice
versa .

 DEVICE CONTROLLED:- Here data transfer is
controlled by IO device . Data is transferred in between
IO device and memory without the intervention of CPU
such a transfer increases rate of transfer and makes the
system more efficient

Here data transfer is controlled by
microprocessor. Microprocessor is primarily
responsible for data transfer whether from
I/o to the CPU or to the memory or vice
versa. Microprocessor based scheme is
further divided into two parts:-

 PROGRAMMED DATA TRANSFER
SCHEME
 INTERRUPT CONTROL DATA TRANSFER
SCHEME

 Program data transfer scheme is controlled
by the CPU . Data are transferred from an IO
device to the CPU or to the memory through
CPU or vice versa under the control of
programs which are stored in memory.
These programs are executed by the CPU
when an I/O device is ready to transfer
data.
 The program data transfer schemes are
employed when small amount of data are to
be transferred.

Here also synchronous and asynchronous mode of
transfer is used.

Synchronous Data Transfer :-

Synchronous means ‘at the same time’. The device
Which sends data and the device which received data are
synchronised with the same clock. When the CPU and
IO devices match in speed, Synchronous Data Transfer
technique is employed.

The data transfer with IO devices is performed by executing IN
and OUT instruction. The IN instruction is used to read data
from an input device or input port. The OUT instruction is used
to sends data from CPU to the output device or output port. As
the CPU and the IO devices match in speed, the I/O device is
ready to transfer data when IN or OUT instruction is executes.
The status of the I/O device, whether it is ready or not, is not
examined before the data is transferred.

Asynchronous mode of transfer :-
Asynchronous means ‘at irregular intervals’. In this
method data transfer is not based on predetermined
timing pattern. This technique of data transfer is used
when the speed of an I/O device does not match
the speed of the microprocessor.

In this technique the status of the I/O device i.e.
whether the device is ready or not, is checked by the
microprocessor before the data are transferred. The
microprocessor initiates the I/O device to get ready
and then continuously checks the status of I/O device
till the I/O device becomes ready to transfer data.
When I/O device becomes ready, the microprocessor
executes instruction to transfer data.

 This mode of data transfer is also called
handshaking mode of data transfer
because some signals are exchanged between
microprocessor and I/O devices before the
actual data transfer takes place. Such signals
are called handshake signals.

 The microprocessor is too busy.
 The CPU is wasting time while checking the
flag instead of doing some useful work.

The problem with programmed I/O is that
CPU has to wait along time for the I/O
device to be ready for reception or
transmission of data .The CPU while
waiting, must repeatedly interrogate the
status of the I/O device . As a result the
level of the performance of the entire
system is severely degraded.
 An alternative is interrupt driven IO
data transfer.

 In this scheme when the I/O device becomes ready
to transfer data, it sends a high signal to the
microprocessor through a special input line called
an interrupt line. In other words it interrupts the
normal processing sequence of the microprocessor.
On receiving interrupt the microprocessor
completes the current instruction, saves the
contents of the program counter on stack first and
then attends the I/O devices. It take up a
subroutine called ISS (Interrupt Service Subroutine).
It execute ISS to transfer data from or to the I/O
device. Different ISS are to be provided for different
IO devices. After completing the data transfer the
microprocessor returns back to the main program
which it was executing before the interrupt
occurred.

 The normal operation of the microprocessor
is interrupted.
 Itneed to continues monitoring for interrupt
signals.

 The transfer of data between the mass
storage device and a system memory is often
limited by the speed of microprocessor.
Removing the microprocessor during such a
transfer and letting the peripheral manage
the transfer to or from memory would
improve the speed of transfer and hence will
make the system more efficient. This transfer
technique is called DMA Data Transfer.

 During DMA transfer microprocessor is idle,
so it has no longer control on the system
buses. A DMA Controller takes over the buses
and manage the transfer directly between the
peripheral and the memory

. It is fastest scheme then
Programmed Data
Transfer Scheme and the
microprocessor regains
the control of buses after
data transfer

Data transferschemes

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