The article presents the study of cryptographic transformations of the Kuznyechik algorithm in relation to differential analysis and the translation of their representations into a more convenient form for cryptanalysis. A simplification of the type of transformations of the algorithm to algebraic the form, in which cryptanalysis software will be more effective. Since the description of the algorithm in the analytical form allows for 16 cycles of execution of the shift register with linear feedback, each of which will be carried out 16 operations of multiplication and 15 operations of addition, reduced to 16 multiplying and 15 the operations of addition. The result is an algebraic form of a linear transformation (from a shift register with linear feedback to the multiplication of the matrix in a finite field). In the future, the algebraic type of transformation can be used to effectively carry out differential cryptanalysis.
This document contains information about graph theory algorithms including:
- Kruskal's algorithm and Prim's algorithm for finding minimum spanning trees. Both algorithms are demonstrated on sample graphs.
- Definitions of Hamiltonian paths, Hamiltonian cycles, and traceable graphs.
- An explanation of Dijkstra's algorithm for finding shortest paths in graphs. Two animated examples of Dijkstra's algorithm are shown step-by-step.
This document is a lecture on digital electronics presented by Dr. Manjunatha. P. It begins with an overview and classification of materials as metals, semiconductors, and insulators based on their resistivity and energy bands. It then discusses semiconductor diodes and their characteristics. The main topics covered include logic gates such as NOT, AND, OR, NAND, NOR, XOR and XNOR gates. Their truth tables and implementations using other gates are provided. Analogies are drawn between logic gates and electrical circuits.
This document provides an overview of digital electronics and logic gates. It begins with classifying materials as metals, semiconductors, or insulators based on their conductivity and energy bands. Common semiconductor devices like diodes, transistors, and their applications in rectifiers are described. The main logic gates - NOT, AND, OR, NAND, NOR, XOR and XNOR - are defined through their truth tables and symbols. Equivalence of different gates using NAND or NOR is also shown. Circuit analogies are provided to explain gate operations.
The Data Acquisition and Processing Based on MEMS AccelerometerIJRES Journal
This document discusses the design of a data acquisition system using a MEMS accelerometer. It includes:
1) A hardware system is designed using an STM32 microprocessor and ADXL345 accelerometer to acquire acceleration data via I2C communication.
2) Software is developed to read acceleration registers, transmit data to a PC, and receive it using a debugging assistant.
3) Data processing techniques are applied including curve fitting to reduce noise and coordinate transformations to eliminate gravity's effect and calculate motion trajectories using double integration of acceleration data.
4) The acceleration data is simulated in MATLAB to generate the trajectory of the input component as it rotates in 3D space.
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document summarizes a presentation on fault detection in the Advanced Encryption Standard (AES) algorithm. It begins with an introduction to AES, which is a symmetric key algorithm that operates on 128-bit blocks using 128, 192, or 256-bit keys. It then discusses related work on improving AES performance and fault detection. The proposed system describes the AES algorithm and its transformations in more detail. A fault detection scheme is proposed that calculates parities of blocks in the AES S-box and inverse S-box. Implementation results show the proposed scheme achieves high error coverage for single and multiple faults with low area and delay costs.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
This document contains information about graph theory algorithms including:
- Kruskal's algorithm and Prim's algorithm for finding minimum spanning trees. Both algorithms are demonstrated on sample graphs.
- Definitions of Hamiltonian paths, Hamiltonian cycles, and traceable graphs.
- An explanation of Dijkstra's algorithm for finding shortest paths in graphs. Two animated examples of Dijkstra's algorithm are shown step-by-step.
This document is a lecture on digital electronics presented by Dr. Manjunatha. P. It begins with an overview and classification of materials as metals, semiconductors, and insulators based on their resistivity and energy bands. It then discusses semiconductor diodes and their characteristics. The main topics covered include logic gates such as NOT, AND, OR, NAND, NOR, XOR and XNOR gates. Their truth tables and implementations using other gates are provided. Analogies are drawn between logic gates and electrical circuits.
This document provides an overview of digital electronics and logic gates. It begins with classifying materials as metals, semiconductors, or insulators based on their conductivity and energy bands. Common semiconductor devices like diodes, transistors, and their applications in rectifiers are described. The main logic gates - NOT, AND, OR, NAND, NOR, XOR and XNOR - are defined through their truth tables and symbols. Equivalence of different gates using NAND or NOR is also shown. Circuit analogies are provided to explain gate operations.
The Data Acquisition and Processing Based on MEMS AccelerometerIJRES Journal
This document discusses the design of a data acquisition system using a MEMS accelerometer. It includes:
1) A hardware system is designed using an STM32 microprocessor and ADXL345 accelerometer to acquire acceleration data via I2C communication.
2) Software is developed to read acceleration registers, transmit data to a PC, and receive it using a debugging assistant.
3) Data processing techniques are applied including curve fitting to reduce noise and coordinate transformations to eliminate gravity's effect and calculate motion trajectories using double integration of acceleration data.
4) The acceleration data is simulated in MATLAB to generate the trajectory of the input component as it rotates in 3D space.
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document summarizes a presentation on fault detection in the Advanced Encryption Standard (AES) algorithm. It begins with an introduction to AES, which is a symmetric key algorithm that operates on 128-bit blocks using 128, 192, or 256-bit keys. It then discusses related work on improving AES performance and fault detection. The proposed system describes the AES algorithm and its transformations in more detail. A fault detection scheme is proposed that calculates parities of blocks in the AES S-box and inverse S-box. Implementation results show the proposed scheme achieves high error coverage for single and multiple faults with low area and delay costs.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
EFFICIENT DIGITAL ENCRYPTION ALGORITHM BASED ON MATRIX SCRAMBLING TECHNIQUEIJNSA Journal
This paper puts forward a safe mechanism of data transmission to tackle the security problem of information which is transmitted in Internet. We propose a new technique on matrix scrambling which is based on random function, shifting and reversing techniques of circular queue. We give statistical analysis, sequence random analysis, and sensitivity analysis to plaintext and key on the proposed scheme. The experimental results show that the new scheme has a very fast encryption speed and the key space is expanded and it can resist all kinds of cryptanalytic, statistical attacks, and especially, our new method can be also used to solve the problem that is easily exposed to chosen plaintext attack. We give our detailed report to this algorithm, and reveal the characteristic of this algorithm by utilizing an example.
SLIDING WINDOW SUM ALGORITHMS FOR DEEP NEURAL NETWORKSIJCI JOURNAL
Sliding window sums are widely used for string indexing, hashing and time series analysis. We have
developed a family of the generic vectorized sliding sum algorithms that provide speedup of O(P/w) for
window size w and number of processors P. For a sum with a commutative operator the speedup is
improved to O(P/log(w)). Even more important, our algorithms exhibit efficient memory access patterns. In
this paper we study the application of sliding sum algorithms to the training and inference of Deep Neural
Networks. We demonstrate how both pooling and convolution primitives could be expressed as sliding
sums and evaluated by the compute kernels with a shared structure. We show that the sliding sum
convolution kernels are more efficient than the commonly used GEMM kernels on CPUs and could even
outperform their GPU counterparts.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
This document discusses a proposed design for secure military communications using AES encryption with Vedic mathematics, OFDM modulation, and QPSK. Specifically, it proposes using AES to encrypt data, applying Vedic math techniques to improve efficiency during the MixColumns step. The encrypted data would then be modulated using OFDM and QPSK to provide high throughput communication. Key aspects of the design include AES encryption/decryption, OFDM using QPSK and an IFFT/FFT, and applying Vedic math during AES encryption to reduce complexity and power consumption for military applications.
FPGA Implementation of an Area Optimized Architecture for 128 bit AES AlgorithmIJERA Editor
This paper aims at FPGA Implementation of an Area Optimized Architecture for 128 bit AES Algorithm. The
conventional designs use a separate module for 32 bit byte substitution and 128 bit byte substitution. The 32 bit
byte substitution is used in round key generation and the 128 bit byte substitution is used in the rounds. This
report presents a modified architecture of 128 bit byte substitution module using a single 32 bit byte substitution
module to reduce area.The AES encryption and decryption algorithm were designed using Verilog HDL. The
functionality of the modules were checked using ModelSim. The simulations were carried out in ModelSim and
Quartus II. The algorithm was implemented in FPGA and achieved a 2% reduction in the total logic element
utilization
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
A design of parity check matrix for short irregular ldpc codes via magicIAEME Publication
This document summarizes a research paper that proposes a new algorithm called the Magic Square Based Algorithm (MSBA) to construct parity check matrices for short irregular low-density parity-check (LDPC) codes. The MSBA applies concepts from magic squares to implicitly generate the cyclic shifts in the parity check matrix in a structured way, rather than using random generation. Simulation results show that codes constructed with the MSBA can achieve a bit error rate of 10-4 at a signal-to-noise ratio of 5 dB with a moderate number of decoding iterations.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
Design and Simulation of a Modified Architecture of Carry Save AdderCSCJournals
This document summarizes a research paper that presents a modified architecture for a carry-save adder. The architecture performs binary addition using a series of XOR, AND, and shift-left operations. A behavioral model was developed in MATLAB to analyze all possible addition combinations for operands up to 15 bits. The model found that the number of shift operations varies from 0 to the number of bits. A mathematical model was derived to predict the average number of shifts for standard operand sizes like 32, 64, or 128 bits. 4-bit synchronous and asynchronous prototypes were designed in Quartus II and simulated to validate the modified adder architecture.
Domain Examination of Chaos Logistics Function As A Key Generator in Cryptogr...IJECEIAES
The use of logistics functions as a random number generator in a cryptography algo- rithm is capable of accommodating the diffusion properties of the Shannon principle. The problem that occurs is initialization x was static and was not affected by changes in the key, so that the algorithm will generate a random number that is always the same. This study design three schemes that can providing the flexibility of the input keys in conducting the examination of the value of the domain logistics function. The results of each schemes do not show a pattern that is directly proportional or inverse with the value of x 0 and relative error x 0 0 and successfully fulfill the properties of the butterfly effect. Thus, the existence of logistics functions in generating chaos numbers can be accommodated based on key inputs. In addition, the resulting random numbers are distributed evenly over the chaos range, thus reinforcing the algorithm when used as a key in cryptography.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
This document discusses the implementation of AES encryption and decryption using a multiplexer look-up table (MLUT) based substitution box (S-box) on an FPGA to reduce power consumption and increase resistance to side channel attacks. The proposed MLUT S-box uses a 256-byte to 1-byte multiplexer with a 256-byte memory to select pre-computed S-box outputs, making it simpler and lower power than conventional implementations. Simulation results show the MLUT S-box design encrypting and decrypting data correctly while consuming 0.55W of power, three times lower than a conventional S-box. Power analysis also found the MLUT S-box has highly uniform power dissipation for different inputs
Improved authenticated elliptic curve cryptography scheme for resource starve...CSITiaesprime
Elliptic curve cryptography (ECC) remains the best approach to asymmetric cryptography when it comes to securing communication among communication partners in low-computing devices such as wireless sensor networks (WSN) and the Internet of Things (IoT) due to its effectiveness in generating small keys with a strong encryption mechanism. The ECC cuts down on power use and improves device performance, so it can be used in a wide range of devices that don't have a lot of resources. However, most of the existing ECC implementations suffer from implementation flaws that make them vulnerable to cryptanalysis attacks. In this study, flaws in the existing implementation of ECC are identified. A new scheme where the identified flaws are remedied was developed. The results of the security analysis show that the new scheme is an indistinguishable authenticated adaptive chosen ciphertext attack (IND-CCA3), resistant to malleability and man-in-the-middle attacks (MIMA). The results of comparative security analysis show that the mapping scheme employed in the new scheme maps any blocks of plaintext to distinct points on an elliptic curve, which makes it resistant to all attacks that the existing schemes are vulnerable to without having a negative effect on its encryption and decryption time, throughput, or power consumption.
Mixed Scanning and DFT Techniques for Arithmetic CoreIJERA Editor
Elliptic curve Cryptosystem used in cryptography chips undergoes side channel threats, where the attackers deciphered the secret key from the scan path. The usage of extra electronic components in scan path architecture will protect the secret key from threats. This work presents a new scan based flip flop for secure cryptographic application. By adding more sensitive internal nets along with the scan enable the testing team can find out the bugs in chip after post-silicon and even after chip fabrication. Also present a new mixed technique by adding DFT(design for testing or Dfx unit) unit and scan unit in same chip unit without affecting the normal critical path ,i.e. without affecting speed of operation of chip, latency in normal mode. Both Scan unit and DFT unit are used for testing the sequential and combinational circuits present in 32 Bit Arithmetic core. Here a proposed PN code generation unit as scan in port to increase the code coverage and scan out port efficiency. The proposed system will written in verilog code and simulated using Xilinx Tool. The hardware module core is synthesized using Xilinx Vertex 5 Field Programmable Gated Array (FPGA) kit. The performance utilization is reported with the help of generated synthesis result
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
This document summarizes a research paper that implemented a pipelined CORDIC architecture in Simulink to generate sine and cosine values. The CORDIC algorithm uses only shift and add operations to perform trigonometric and other elementary functions. It was applied here in rotation mode to simultaneously compute sine and cosine of an input angle. A 12-stage pipelined CORDIC architecture was modeled in Simulink. The shifts and constants were hardwired to reduce resources and latency. Testing with an input of 0.6 radians showed accurate outputs for sine and cosine. The implementation demonstrated the utility of Simulink for modeling hardware systems and algorithms like CORDIC.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
A vlsi implementation of a resource efficient and secure architecture of a b...eSAT Journals
Abstract
In today‘s modern life, the protection of data is of major concern in any kind of domian. So the understanding of cryptography architecture plays a crucial role. Advance encryption system , differential encryption system design of cryptography have few drawbacks in implementation level of low level designs. In an area concerned and power concerned parameters the above mentioned algorithms have failed in implementing. The humming bird algorithm uses block cipher which is being used in this paper for encryption and decryption using 128 bit secure key. Block cipher concentrates on converting the given original data into cipher text to make the given data more secure over the user. Two different designs of block Cipher algorithms (Throughput enhanced , Area reduced) are developed and their performance is compared in terms of area occupation using Xilinx ISE design tool with verilog language. The block cipher designs are implemented using 64 bit secure key and 128 bit secure key. The area reduced design is of the concern to have this module on the FPGA implementation in the VLSI sector.
Keywords : Cryptography, VLSI, FPGA , Block Cipher.
A vlsi implementation of a resource efficient and secure architecture of a b...eSAT Journals
This document discusses the VLSI implementation of a resource efficient and secure architecture for a block cipher. It proposes two designs - a throughput enhanced design and an area reduced design. The designs implement a 128-bit block cipher using the Hummingbird algorithm. Simulation results on ModelSim and synthesis results on Xilinx show that the area reduced design uses fewer logic resources than the throughput enhanced design, making it more suitable for FPGA implementation where area is a concern.
IRJET - Multi-Key Privacy in Cloud ComputingIRJET Journal
The document describes a proposed system for secure data exchange and storage in the cloud using an Android application. The system utilizes AES, RSA, and HMAC cryptographic techniques to encrypt data before uploading it to a Firebase cloud storage platform. AES is used for file encryption, RSA is used for key exchange, and HMAC is used for authentication. The Android application provides an interface for users to select files to encrypt on their device, set an encryption key, and upload the encrypted files to the cloud for secure backup and access from other devices. The system aims to ensure confidentiality, integrity, authentication and non-repudiation of data in the cloud.
DEVELOPMENT OF TODDLER FAMILY CADRE TRAINING BASED ON ANDROID APPLICATIONS IN...AM Publications
Toddler family cadre is a community members work voluntarily in fostering and providing information to parents of toddlers about how to properly care for children. Toddler Family cadre desperately need training to increase their skills. There are still a few Toddler family cadres who get training so that the knowledge and skills of parents and other family members in developing toddlers' growth through physical stimulation, motoric intelligence, emotional and social economy as well as possible are still lacking. The purpose of this study is to develop an Android- assisted Toddler family cadre training model in Demak. This research is research in tian research and development. The research location was in Demak Regency. Toddler family cadres became the object of this research. Development of Toddler family cadre training models assisted by Android in Demak is feasible to be used as an effort to improve Toddler Family cadres' capabilities.
TESTING OF COMPOSITE ON DROP-WEIGHT IMPACT TESTING AND DAMAGE IDENTIFICATION ...AM Publications
In recent years the use of composite materials in structural components has become increasingly common in a wide range of engineering applications. Composite materials offer numerous advantages over more conventional materials because of their superior specific properties, but a serious obstacle to a more widespread use of these materials is their high sensitivity to localized impact loading. This paper presents an experimental study to assess the impact response of drop weight impact tests on fiber reinforced polymer composites with deferent load and damage identification of composite using Non-destructive testing techniques ultrasonic testing (UT) C scan. In the study includes checking the strength of the specimen, plotting of graphs between the height and the impact energy obtained and tabulating the results after conducting the various functional tests.
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CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
EFFICIENT DIGITAL ENCRYPTION ALGORITHM BASED ON MATRIX SCRAMBLING TECHNIQUEIJNSA Journal
This paper puts forward a safe mechanism of data transmission to tackle the security problem of information which is transmitted in Internet. We propose a new technique on matrix scrambling which is based on random function, shifting and reversing techniques of circular queue. We give statistical analysis, sequence random analysis, and sensitivity analysis to plaintext and key on the proposed scheme. The experimental results show that the new scheme has a very fast encryption speed and the key space is expanded and it can resist all kinds of cryptanalytic, statistical attacks, and especially, our new method can be also used to solve the problem that is easily exposed to chosen plaintext attack. We give our detailed report to this algorithm, and reveal the characteristic of this algorithm by utilizing an example.
SLIDING WINDOW SUM ALGORITHMS FOR DEEP NEURAL NETWORKSIJCI JOURNAL
Sliding window sums are widely used for string indexing, hashing and time series analysis. We have
developed a family of the generic vectorized sliding sum algorithms that provide speedup of O(P/w) for
window size w and number of processors P. For a sum with a commutative operator the speedup is
improved to O(P/log(w)). Even more important, our algorithms exhibit efficient memory access patterns. In
this paper we study the application of sliding sum algorithms to the training and inference of Deep Neural
Networks. We demonstrate how both pooling and convolution primitives could be expressed as sliding
sums and evaluated by the compute kernels with a shared structure. We show that the sliding sum
convolution kernels are more efficient than the commonly used GEMM kernels on CPUs and could even
outperform their GPU counterparts.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
This document discusses a proposed design for secure military communications using AES encryption with Vedic mathematics, OFDM modulation, and QPSK. Specifically, it proposes using AES to encrypt data, applying Vedic math techniques to improve efficiency during the MixColumns step. The encrypted data would then be modulated using OFDM and QPSK to provide high throughput communication. Key aspects of the design include AES encryption/decryption, OFDM using QPSK and an IFFT/FFT, and applying Vedic math during AES encryption to reduce complexity and power consumption for military applications.
FPGA Implementation of an Area Optimized Architecture for 128 bit AES AlgorithmIJERA Editor
This paper aims at FPGA Implementation of an Area Optimized Architecture for 128 bit AES Algorithm. The
conventional designs use a separate module for 32 bit byte substitution and 128 bit byte substitution. The 32 bit
byte substitution is used in round key generation and the 128 bit byte substitution is used in the rounds. This
report presents a modified architecture of 128 bit byte substitution module using a single 32 bit byte substitution
module to reduce area.The AES encryption and decryption algorithm were designed using Verilog HDL. The
functionality of the modules were checked using ModelSim. The simulations were carried out in ModelSim and
Quartus II. The algorithm was implemented in FPGA and achieved a 2% reduction in the total logic element
utilization
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
A design of parity check matrix for short irregular ldpc codes via magicIAEME Publication
This document summarizes a research paper that proposes a new algorithm called the Magic Square Based Algorithm (MSBA) to construct parity check matrices for short irregular low-density parity-check (LDPC) codes. The MSBA applies concepts from magic squares to implicitly generate the cyclic shifts in the parity check matrix in a structured way, rather than using random generation. Simulation results show that codes constructed with the MSBA can achieve a bit error rate of 10-4 at a signal-to-noise ratio of 5 dB with a moderate number of decoding iterations.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
Design and Simulation of a Modified Architecture of Carry Save AdderCSCJournals
This document summarizes a research paper that presents a modified architecture for a carry-save adder. The architecture performs binary addition using a series of XOR, AND, and shift-left operations. A behavioral model was developed in MATLAB to analyze all possible addition combinations for operands up to 15 bits. The model found that the number of shift operations varies from 0 to the number of bits. A mathematical model was derived to predict the average number of shifts for standard operand sizes like 32, 64, or 128 bits. 4-bit synchronous and asynchronous prototypes were designed in Quartus II and simulated to validate the modified adder architecture.
Domain Examination of Chaos Logistics Function As A Key Generator in Cryptogr...IJECEIAES
The use of logistics functions as a random number generator in a cryptography algo- rithm is capable of accommodating the diffusion properties of the Shannon principle. The problem that occurs is initialization x was static and was not affected by changes in the key, so that the algorithm will generate a random number that is always the same. This study design three schemes that can providing the flexibility of the input keys in conducting the examination of the value of the domain logistics function. The results of each schemes do not show a pattern that is directly proportional or inverse with the value of x 0 and relative error x 0 0 and successfully fulfill the properties of the butterfly effect. Thus, the existence of logistics functions in generating chaos numbers can be accommodated based on key inputs. In addition, the resulting random numbers are distributed evenly over the chaos range, thus reinforcing the algorithm when used as a key in cryptography.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
This document discusses the implementation of AES encryption and decryption using a multiplexer look-up table (MLUT) based substitution box (S-box) on an FPGA to reduce power consumption and increase resistance to side channel attacks. The proposed MLUT S-box uses a 256-byte to 1-byte multiplexer with a 256-byte memory to select pre-computed S-box outputs, making it simpler and lower power than conventional implementations. Simulation results show the MLUT S-box design encrypting and decrypting data correctly while consuming 0.55W of power, three times lower than a conventional S-box. Power analysis also found the MLUT S-box has highly uniform power dissipation for different inputs
Improved authenticated elliptic curve cryptography scheme for resource starve...CSITiaesprime
Elliptic curve cryptography (ECC) remains the best approach to asymmetric cryptography when it comes to securing communication among communication partners in low-computing devices such as wireless sensor networks (WSN) and the Internet of Things (IoT) due to its effectiveness in generating small keys with a strong encryption mechanism. The ECC cuts down on power use and improves device performance, so it can be used in a wide range of devices that don't have a lot of resources. However, most of the existing ECC implementations suffer from implementation flaws that make them vulnerable to cryptanalysis attacks. In this study, flaws in the existing implementation of ECC are identified. A new scheme where the identified flaws are remedied was developed. The results of the security analysis show that the new scheme is an indistinguishable authenticated adaptive chosen ciphertext attack (IND-CCA3), resistant to malleability and man-in-the-middle attacks (MIMA). The results of comparative security analysis show that the mapping scheme employed in the new scheme maps any blocks of plaintext to distinct points on an elliptic curve, which makes it resistant to all attacks that the existing schemes are vulnerable to without having a negative effect on its encryption and decryption time, throughput, or power consumption.
Mixed Scanning and DFT Techniques for Arithmetic CoreIJERA Editor
Elliptic curve Cryptosystem used in cryptography chips undergoes side channel threats, where the attackers deciphered the secret key from the scan path. The usage of extra electronic components in scan path architecture will protect the secret key from threats. This work presents a new scan based flip flop for secure cryptographic application. By adding more sensitive internal nets along with the scan enable the testing team can find out the bugs in chip after post-silicon and even after chip fabrication. Also present a new mixed technique by adding DFT(design for testing or Dfx unit) unit and scan unit in same chip unit without affecting the normal critical path ,i.e. without affecting speed of operation of chip, latency in normal mode. Both Scan unit and DFT unit are used for testing the sequential and combinational circuits present in 32 Bit Arithmetic core. Here a proposed PN code generation unit as scan in port to increase the code coverage and scan out port efficiency. The proposed system will written in verilog code and simulated using Xilinx Tool. The hardware module core is synthesized using Xilinx Vertex 5 Field Programmable Gated Array (FPGA) kit. The performance utilization is reported with the help of generated synthesis result
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
This document summarizes a research paper that implemented a pipelined CORDIC architecture in Simulink to generate sine and cosine values. The CORDIC algorithm uses only shift and add operations to perform trigonometric and other elementary functions. It was applied here in rotation mode to simultaneously compute sine and cosine of an input angle. A 12-stage pipelined CORDIC architecture was modeled in Simulink. The shifts and constants were hardwired to reduce resources and latency. Testing with an input of 0.6 radians showed accurate outputs for sine and cosine. The implementation demonstrated the utility of Simulink for modeling hardware systems and algorithms like CORDIC.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
A vlsi implementation of a resource efficient and secure architecture of a b...eSAT Journals
Abstract
In today‘s modern life, the protection of data is of major concern in any kind of domian. So the understanding of cryptography architecture plays a crucial role. Advance encryption system , differential encryption system design of cryptography have few drawbacks in implementation level of low level designs. In an area concerned and power concerned parameters the above mentioned algorithms have failed in implementing. The humming bird algorithm uses block cipher which is being used in this paper for encryption and decryption using 128 bit secure key. Block cipher concentrates on converting the given original data into cipher text to make the given data more secure over the user. Two different designs of block Cipher algorithms (Throughput enhanced , Area reduced) are developed and their performance is compared in terms of area occupation using Xilinx ISE design tool with verilog language. The block cipher designs are implemented using 64 bit secure key and 128 bit secure key. The area reduced design is of the concern to have this module on the FPGA implementation in the VLSI sector.
Keywords : Cryptography, VLSI, FPGA , Block Cipher.
A vlsi implementation of a resource efficient and secure architecture of a b...eSAT Journals
This document discusses the VLSI implementation of a resource efficient and secure architecture for a block cipher. It proposes two designs - a throughput enhanced design and an area reduced design. The designs implement a 128-bit block cipher using the Hummingbird algorithm. Simulation results on ModelSim and synthesis results on Xilinx show that the area reduced design uses fewer logic resources than the throughput enhanced design, making it more suitable for FPGA implementation where area is a concern.
IRJET - Multi-Key Privacy in Cloud ComputingIRJET Journal
The document describes a proposed system for secure data exchange and storage in the cloud using an Android application. The system utilizes AES, RSA, and HMAC cryptographic techniques to encrypt data before uploading it to a Firebase cloud storage platform. AES is used for file encryption, RSA is used for key exchange, and HMAC is used for authentication. The Android application provides an interface for users to select files to encrypt on their device, set an encryption key, and upload the encrypted files to the cloud for secure backup and access from other devices. The system aims to ensure confidentiality, integrity, authentication and non-repudiation of data in the cloud.
Similar to REPRESENTATION OF THE BLOCK DATA ENCRYPTION ALGORITHM IN AN ANALYTICAL FORM FOR DIFFERENTIAL CRYPTANALYSIS (20)
DEVELOPMENT OF TODDLER FAMILY CADRE TRAINING BASED ON ANDROID APPLICATIONS IN...AM Publications
Toddler family cadre is a community members work voluntarily in fostering and providing information to parents of toddlers about how to properly care for children. Toddler Family cadre desperately need training to increase their skills. There are still a few Toddler family cadres who get training so that the knowledge and skills of parents and other family members in developing toddlers' growth through physical stimulation, motoric intelligence, emotional and social economy as well as possible are still lacking. The purpose of this study is to develop an Android- assisted Toddler family cadre training model in Demak. This research is research in tian research and development. The research location was in Demak Regency. Toddler family cadres became the object of this research. Development of Toddler family cadre training models assisted by Android in Demak is feasible to be used as an effort to improve Toddler Family cadres' capabilities.
TESTING OF COMPOSITE ON DROP-WEIGHT IMPACT TESTING AND DAMAGE IDENTIFICATION ...AM Publications
In recent years the use of composite materials in structural components has become increasingly common in a wide range of engineering applications. Composite materials offer numerous advantages over more conventional materials because of their superior specific properties, but a serious obstacle to a more widespread use of these materials is their high sensitivity to localized impact loading. This paper presents an experimental study to assess the impact response of drop weight impact tests on fiber reinforced polymer composites with deferent load and damage identification of composite using Non-destructive testing techniques ultrasonic testing (UT) C scan. In the study includes checking the strength of the specimen, plotting of graphs between the height and the impact energy obtained and tabulating the results after conducting the various functional tests.
THE USE OF FRACTAL GEOMETRY IN TILING MOTIF DESIGNAM Publications
In this paper I will present the use of fractal geometry to design tile motifs. A fractal is a geometric figure that combines the several characteristics among others: its parts have the same form as the whole, fragmented, and formation by iteration. The concept of fractals has been spread over all fields of sciences, technology, and art. This paper aims to provide an algorithm to creating motifs of tile algorithm for create the tile motif consists of base, iteration, coloration and duplication. In order to help the reader better understand the algorithm, I will present some script using Matlab. We describe a mathematically based algorithm that can fill a spatial region with sequence of randomly placed which may be transformed copies of one motif or several motifs. By using this algorithm, I can produce thousand variety of aesthetically pleasing tile motifs, of which we show a number of examples.
TWO-DIMENSIONAL INVERSION FINITE ELEMENT MODELING OF MAGNETOTELLURIC DATA: CA...AM Publications
Two-dimensional resistivity analysis of magnetotelluric data has been done at “Z” geothermal area which is located in southern part of Indonesia. The objective is to understand subsurface structure beneath reasearch area based on 2-D modeling of magnetotelluric data. The inversion finite element method were used for numerical simulations which requires discretization on the boundary of the modeling domain. The modeling results of magnetotelluric data shows relativity structure dissemination: 0-10 ohm.m in a thickness of 1 km (Clay Cap), 10-100 ohm.m with 1-2 km depth respectively (reservoir zone), and on a scale of 100-1000 ohm.m in a depth of 2-3 km (heat source zone). The result of relativity structure can be used to delineate an area with geothermal prospect around 12 km2.
USING THE GENETIC ALGORITHM TO OPTIMIZE LASER WELDING PARAMETERS FOR MARTENSI...AM Publications
This document presents an optimization of laser welding parameters for martensitic stainless steel using a genetic algorithm. The algorithm aims to minimize the difference between the actual and desired weld size (width and depth) by optimizing laser power, welding speed, and fiber diameter. The genetic algorithm was run 10 times with a population of 30 over 200 iterations each time. The results showed errors between optimized and experimental values of less than 5% for the parameters. The study demonstrates that genetic algorithms can effectively optimize laser welding parameters to achieve a preset weld size.
ANALYSIS AND DESIGN E-MARKETPLACE FOR MICRO, SMALL AND MEDIUM ENTERPRISESAM Publications
The Ministry of Cooperatives and Small and Medium Enterprises launched in 2018 the number of Micro, Small and Medium Enterprises (MSMEs) in Indonesia as many as 58.97 million people. It is predicted that the number of MSMEs players in 2019 will amount to 59.2 million. This shows that the Indonesian people have made changes in the field of family economics which initially as consumptive are now productive. The community prefers to carry out activities that can increase family income. Future MSMEs remain the mainstay of the national economy. In accordance with the government roadmap, in 2020 e-commerce transactions are predicted to reach Rp1,300 trillion or equivalent to USD130 billion. According to data from the Central Statistics Agency (BPS), the contribution of MSMEs to Indonesia's Gross Domestic Product (GDP) reached 61.41%, with the number of MSMEs reaching almost 60 million units. However, only around 8% or 3.79 million of the 59.2 million MSMEs players have used online platforms to market their products. Based on the above problems, researchers conducted research on the analysis and display of E-Marketplace for MSMEs in Indonesia. The type of research used is action research. The object of research is MSMEs which are under the Office of Industry and Trade of Sragen Regency. The method of data collection is by techniques: (1) interview, (2) documentation (3) observation, (4) literature study. The researcher uses the waterfall method in developing the system. The research team has successfully analyzed the E-Market place according to the results of data collection. The research team has succeeded in designing the E-Marketplace for MSMEs. E-Marketplace designed can be used by admin, MSME and user. Admin is in charge of managing E-Marketplace and has full access rights. MSMEs can register online and manage their products in E-Marketplace. Users or buyers can search data in E-Marketplace as desired. To make transactions, users can interact directly with MSMEs according to the data provided in E-Marketplace. E-Marketplace can be used for marketing together MSMEs products. This e-marketplace can be accessed at www.umkmonline.com
REMOTE SENSING AND GEOGRAPHIC INFORMATION SYSTEMS AM Publications
Remote sensing technology's increasing accessibility helps us observe research and learn about our globe in ways we could only imagine a generation ago. Guides to profound knowledge of historical, conceptual and practical uses of remote sensing which is increasing GIS technology. This paper will go briefly through remote sensing benefits, history, technology and the GIS and remote sensing integration and their applications. Remote sensing (RS) is used in mapping the predicted and actual species and dominates the ecosystem canopy.
EVALUATE THE STRAIN ENERGY ERROR FOR THE LASER WELD BY THE H-REFINEMENT OF TH...AM Publications
Currently, the finite element method (FEM) is still one of the useful tools in numerical simulation for technical problems. With this method, a continuum model presented by a certain number of elements with a simple approximation field causes the presence of discretization error in solutions. This paper considers the butt weld by laser which subjected the tension for AISI 1018 steel highness 8 mm. The aim of the study is to use the h-refinement of the FEM in estimation the strain energy error for the laser weld mentioned. The results show that the stability of the h-refinement shown by the value of the relative error of the strain energy is quite small, specifically; FEM is less than 5.7% and extra is no more than 3.7%.
HMM APPLICATION IN ISOLATED WORD SPEECH RECOGNITIONAM Publications
Speech recognition is always being an all-time trendy topic for discussion and also for researches and we see a major application in our life. This paper provides the work done on the application of Hidden Markov model to implement isolated word speech recognition on MATLAB and to develop and train the system for set of self-selective words for specific user (user dependent) to get maximum efficiency in word recognition system. Which uses the forward and Baum-welch algorithm and fitting Gaussian of the Baum-welch algorithm for all the iteration perform. We use a sample of 7 alphabets which are recorded in 15 different ways giving total of 105 word to use for training with each word with 15 variations. This system can be used in real world in system security using voice security system and mainly for children and impaired people.
PEDESTRIAN DETECTION IN LOW RESOLUTION VIDEOS USING A MULTI-FRAME HOG-BASED D...AM Publications
Detecting pedestrians in low resolution videos is a challenging task, due to the small size of pedestrians in the images and the limited information. In practical outdoor surveillance scenarios the pedestrian size is usually small. Existing state-of-the-art pedestrian detection methods that use histogram of oriented gradient (HOG) features have poor performance in this problem domain. To compensate for the lack of information in a single frame, we propose a novel detection method that recognizes pedestrians in a short sequence of frames. Namely, we take the single-frame HOG-based detector and extend it to multiple frames. Our detector is applied to regions containing potential moving objects. In the case of video taken from a moving camera on an aerial platform, video stabilization is first performed to register the frames. A classifier is then applied to features extracted from spatio-temporal volumes surrounding the potential moving objects. On challenging stationary and aerial video datasets, our detection accuracy outperforms several state-of-the-art algorithms.
The aim of this paper is to help the blind people to identify and catch the public transport vehicles with the help of Light Fidelity technology. It is a Navigation aid. When the bus arrives at the bus stand, transmitter in the bus transmits the light signals and receiver in the stick, receives the light signals and a sound signal is generated through the speaker present in the stick. The sound message contains the bus number and the destination of the bus. In addition to this, if the person is absconded or lost, details of the location will be sent to his/her family members by pressing a button. This is made possible with the help of Global System for Mobile (GSM). Finally, presence of water can be detected along the blind person’s path, with the help of water sensors.
EFFECT OF SILICON - RUBBER (SR) SHEETS AS AN ALTERNATIVE FILTER ON HIGH AND L...AM Publications
A digital radiography delivers a radiation dose to patients; therefore it poses potential risk to the patients. One effort to reduce dose is carried out using a radiation filter, e.g. Silicone Rubber (SR) sheet. The purpose of this research was to determine the impact of the SR sheet on the high contrast objects (HCO) and the low contrast objects (LCO). The dose reduction was determined from attenuation x-rays before and after using the SR sheet. Assessment of HCO and LCO was observed from CDR TOR phantom at tube voltage of 48 kVp and tube current of 8 mAs. The physical parameter to assess image quality was the Signal to Noise Ratio (SNR) value in LCO. The maximum x-ray attenuation using the SR sheet is 48.82%. The visibility of the HCO remains the same, namely 16 objects; however the LCO slighly decreases from 14 objects to 13 objects after using the SR sheet. The SNR value decreases with an average value of 15.17%.Therefore, the SR sheet as a alternative filter has no effect on the HCO and has realtively little effect on the LCO. Thus, the SR sheet potentially is used for radiation protection in patients, especially on examinations that do not require low contrast resolution.
UTILIZATION OF IMMUNIZATION SERVICES AMONG CHILDREN UNDER FIVE YEARS OF AGE I...AM Publications
Immunization is the key strategy to curb communicable diseases which are the number one killer of children under five. Immunization prevents mortalities of approximating three million children under five annually. This study aimed to assess utilization of immunization services among children under five of age in Kirinyaga County, Kenya.
Optical character recognition (OCR) is process of classification of optical patterns contained in a digital image. The process of OCR Recognition involves several steps including pre-processing, segmentation, feature extraction, classification. Pre-processing is for done the basic operation on input image like noise reduction which remove the noisy signal from image. Segmentation stage for segment the given image into line by line and segment each character from segmented line. Future extraction calculates the characteristics of character. A Radial Basis Function Neural Network (RBFNN) is used to classification contains the database and does the comparison.
Surveillance refers to the task of observing a scene, often for lengthy periods in search of particular objects or particular behaviour. This task has many applications, foremost among them is security (monitoring for undesirable behaviour such as theft or vandalism), but increasing numbers of others in areas such as agriculture also exist. Historically, closed circuit TV (CCTV) surveillance has been mundane and labour Intensive, involving personnel scanning multiple screens, but the advent of reasonably priced fast hardware means that automatic surveillance is becoming a realistic task to attempt in real time. Several attempts at this are underway.
SIMULATION OF ATMOSPHERIC POLLUTANTS DISPERSION IN AN URBAN ENVIRONMENTAM Publications
Interest in air pollution investigation of urban environment due to existence of industrial and commercial activities along with vehicular emission and existence of buildings and streets which setup natural barrier for pollutant dispersion in the urban environment has increased. The air pollution modelling is a multidisciplinary subject when the entire cities are taken under consideration where urban planning and geometries are complex which needs a large software packages to be developed like Operational Street Pollution Model (OSPM), California Line Source model (CALINE series) etc. On overviewing various works it can be summarized that the air pollutant dispersion in urban street canyons and all linked phenomenon such as wind flow, pollutant concentrations, temperature distribution etc. generally depend on wind speed and direction, building heights and density, road width, source and intensity of air pollution, meteorological variables like temperature, humidity etc. A unique and surprising case is observed every time on numerous combinations of these factors. The main aim of this study is to simulate the atmospheric pollutant dispersion for given pollutant like carbon monoxide, sulphur dioxide and nitrogen dioxide and given atmospheric conditions like wind speed and direction. Computational Fluid Dynamics (CFD) simulation for analysing the atmospheric pollutant dispersion is done after natural airflow analysis. Volume rendering is done for variables such as phase 2 volume fraction and velocity with resolution as 250 pixels per inch and transparency as 20%. It can be observed that all the three pollutant namely nitrogen dioxide, sulphur dioxide and carbon monoxide the phase 2 volume fraction changes from 0 to 1. The wind velocity changes from 3.395×10-13 m/s to 1.692×102 m/s. The dispersion of pollutants follow the sequence Sulphur dioxide>Carbon monoxide>Nitrogen dioxide.
PREPARATION AND EVALUATION OF WOOL KERATIN BASED CHITOSAN NANOFIBERS FOR AIR ...AM Publications
In this article, we have extracted keratin from deccani wool waste and prepared the wool keratin based Chitosan nanofibers by electrospinning technique. The prepared nanofibers mat were prepared with different weight percent ratio like 1wt.%, 3wt.% and 5wt.% with respect to polymer i.e Chitosan. The physicochemical and filtration properties of wool keratin based Chitosan nanofibers were studied. Wool keratin based Chitosan nanofibers were characterized by Fourier transform infrared spectroscopy (FTIR), X-ray diffraction (XRD), differential scanning calorimetry (DSC) and scanning electron microscopy (FESEM). The filtration efficiency of keratin Chitosan nanofibers were investigated through DOP test and heavy metal removal capacity of evaluated through Atomic absorption spectroscopy. FTIR results were showed that Keratin gets compatible with Chitosan. XRD patterns revealed keratin was in crystalline nature and increase the crystalline nature of Chitosan nanofibers. FESEM images showed that uniform nanofibers generation with average fiber diameter 80nm. Nanofibers filtration efficiency against a particulate matter in air was obtained more than 99.53% and excellent property of removal of heavy metal.
ANALYSIS ON LOAD BALANCING ALGORITHMS IMPLEMENTATION ON CLOUD COMPUTING ENVIR...AM Publications
Cloud computing means storing and accessing data and programs over the Internet instead of your computer's hard drive. The cloud is just a metaphor for the Internet. The elements involved in cloud computing are clients, data center and distributed server. One of the main problems in cloud computing is load balancing. Balancing the load means to distribute the workload among several nodes evenly so that no single node will be overloaded. Load can be of any type that is it can be CPU load, memory capacity or network load. In this paper we presented an architecture of load balancing and algorithm which will further improve the load balancing problem by minimizing the response time. In this paper, we have proposed the enhanced version of existing regulated load balancing approach for cloud computing by comping the Randomization and greedy load balancing algorithm. To check the performance of proposed approach, we have used the cloud analyst simulator (Cloud Analyst). Through simulation analysis, it has been found that proposed improved version of regulated load balancing approach has shown better performance in terms of cost, response time and data processing time.
A MODEL BASED APPROACH FOR IMPLEMENTING WLAN SECURITY AM Publications
This paper presents various security features and configurations commonly implemented in WLANs and their aggregated security levels and then proposes a model that enables implementation and evaluation of WLAN security
DATA MINING WITH CLUSTERING ON BIG DATA FOR SHOPPING MALL’S DATASETAM Publications
Big Data is the extremely large sets of data that their sizes are beyond the ability of capturing, managing, processing and storage by most software tools and people which is ever increasing day-by-day. In most enterprise scenarios the data is too big or it moves too fast that extremely exceeds current processing capacity. The term big data is also used by vendors, may refer to the technology which includes tools and processes that an organization requires to handle the large amounts of data and storage facilities. This advancement in technology leads to make relationship marketing a reality for today’s competitive world. But at the same time this huge amount of data cannot be analyzed in a traditional manner, by using manual data analysis. For this, technologies such as data warehousing and data mining have made customer relationship management as a new area where business firms can gain a competitive advantage for identifying their customer behaviors and needs. This paper mainly focuses on data mining technique that performs the extraction of hidden predictive information from large databases and organizations can identify valuable customers and predicts future user behaviors. This enables different organizations to make proactive, knowledge-driven decisions. Data mining tools answer business questions that in the past were too time-consuming, this makes customer relationship management possible. For this in this paper, we are trying explain the use of data mining technique to accomplish the goals of today’s customer relationship management and Decision making for different companies that deals with big data.
Better Builder Magazine brings together premium product manufactures and leading builders to create better differentiated homes and buildings that use less energy, save water and reduce our impact on the environment. The magazine is published four times a year.
Cricket management system ptoject report.pdfKamal Acharya
The aim of this project is to provide the complete information of the National and
International statistics. The information is available country wise and player wise. By
entering the data of eachmatch, we can get all type of reports instantly, which will be
useful to call back history of each player. Also the team performance in each match can
be obtained. We can get a report on number of matches, wins and lost.
Sachpazis_Consolidation Settlement Calculation Program-The Python Code and th...Dr.Costas Sachpazis
Consolidation Settlement Calculation Program-The Python Code
By Professor Dr. Costas Sachpazis, Civil Engineer & Geologist
This program calculates the consolidation settlement for a foundation based on soil layer properties and foundation data. It allows users to input multiple soil layers and foundation characteristics to determine the total settlement.
Online train ticket booking system project.pdfKamal Acharya
Rail transport is one of the important modes of transport in India. Now a days we
see that there are railways that are present for the long as well as short distance
travelling which makes the life of the people easier. When compared to other
means of transport, a railway is the cheapest means of transport. The maintenance
of the railway database also plays a major role in the smooth running of this
system. The Online Train Ticket Management System will help in reserving the
tickets of the railways to travel from a particular source to the destination.