This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
This document describes the design and implementation of a low power 16-bit carry-lookahead adder using two-phase clocked adiabatic static CMOS (2PASCL) logic. 2PASCL circuits can recover energy stored at output nodes during state transitions, providing power savings over conventional CMOS. The authors designed inverters, NAND, NOR, XOR gates and 4, 8, 16-bit carry-lookahead adders using 2PASCL logic in Cadence. Simulation results showed the 2PASCL designs consumed less power than equivalent static CMOS designs. Layouts were also produced for the 4, 8, 16-bit adders. Power analysis confirmed the 2PASCL adders achieved significant
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...IOSRJVSP
This paper presents implementation of Arithmetic Logic Unit as it is fundamental building block of various computing circuits. 4 bit ALU is designed using Modified Quasi State Energy Recovery Logic (MQSERL) and CMOS logic. For implementing ALU, circuits which are needed are Multiplexer , Full adder and various basic gates such as Inverter ,XOR, AND and OR are designed using both logic style. Comparative power analysis has been done to validate the Proposed MQSERL logic style which gives less power dissipation compared to conventional logic. The Arithmetic and Logic Unit designed using proposed MQSERL logic is 24.14 % and 33.28% power efficient than CMOS logic . The operating voltages for all the circuits are 1.8V and simulated using 180nm tanner technology. For MQSERL circuits, two sinusoidal power clock which are 1800 phase shifted with each other are used by maintaining frequency at 100MHz and frequency of the input signal maintained at 50 MHz
This document summarizes a research paper that proposes a non-isolated three-port DC-DC converter with improved time response and steady-state output. The converter uses a single inductor and switched capacitors to achieve high voltage gain with minimal switches. A fuzzy logic controller is proposed for the closed-loop system to further improve the time domain response compared to a PI controller. Simulation results show that the fuzzy logic controller reduces output ripple voltage and improves various time response specifications like rise time, peak time, and settling time. The converter is suitable as an interface between a photovoltaic source, battery backup, and load.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
This paper presents a new topology for cascaded H-bridge multilevel inverter utilizing multicarrier modulation technique. The new five-level topology utilizes a capacitive divider network consisting of two capacitors for producing output voltage levels. The developed circuit has reduced number of switches and dc sources compared to conventional five level inverters. Five main power switches, a single additional diode apart from antiparallel diodes, two capacitors and a dc supply constitute a single five level unit. Simulations as well as experimental results are verified for the new topology utilising multicarrier modulation technique with reduced harmonic distortions in the output.
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
This document describes the design and implementation of a low power 16-bit carry-lookahead adder using two-phase clocked adiabatic static CMOS (2PASCL) logic. 2PASCL circuits can recover energy stored at output nodes during state transitions, providing power savings over conventional CMOS. The authors designed inverters, NAND, NOR, XOR gates and 4, 8, 16-bit carry-lookahead adders using 2PASCL logic in Cadence. Simulation results showed the 2PASCL designs consumed less power than equivalent static CMOS designs. Layouts were also produced for the 4, 8, 16-bit adders. Power analysis confirmed the 2PASCL adders achieved significant
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...IOSRJVSP
This paper presents implementation of Arithmetic Logic Unit as it is fundamental building block of various computing circuits. 4 bit ALU is designed using Modified Quasi State Energy Recovery Logic (MQSERL) and CMOS logic. For implementing ALU, circuits which are needed are Multiplexer , Full adder and various basic gates such as Inverter ,XOR, AND and OR are designed using both logic style. Comparative power analysis has been done to validate the Proposed MQSERL logic style which gives less power dissipation compared to conventional logic. The Arithmetic and Logic Unit designed using proposed MQSERL logic is 24.14 % and 33.28% power efficient than CMOS logic . The operating voltages for all the circuits are 1.8V and simulated using 180nm tanner technology. For MQSERL circuits, two sinusoidal power clock which are 1800 phase shifted with each other are used by maintaining frequency at 100MHz and frequency of the input signal maintained at 50 MHz
This document summarizes a research paper that proposes a non-isolated three-port DC-DC converter with improved time response and steady-state output. The converter uses a single inductor and switched capacitors to achieve high voltage gain with minimal switches. A fuzzy logic controller is proposed for the closed-loop system to further improve the time domain response compared to a PI controller. Simulation results show that the fuzzy logic controller reduces output ripple voltage and improves various time response specifications like rise time, peak time, and settling time. The converter is suitable as an interface between a photovoltaic source, battery backup, and load.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
This paper presents a new topology for cascaded H-bridge multilevel inverter utilizing multicarrier modulation technique. The new five-level topology utilizes a capacitive divider network consisting of two capacitors for producing output voltage levels. The developed circuit has reduced number of switches and dc sources compared to conventional five level inverters. Five main power switches, a single additional diode apart from antiparallel diodes, two capacitors and a dc supply constitute a single five level unit. Simulations as well as experimental results are verified for the new topology utilising multicarrier modulation technique with reduced harmonic distortions in the output.
This document presents a new dual dynamic node hybrid flip-flop (DDFF) and embedded logic module (DDFF-ELM) designed to reduce power consumption in VLSI circuits. The DDFF splits the dynamic node to separately drive the pull-up and pull-down transistors, eliminating large capacitance. The DDFF-ELM incorporates logic functions into the flip-flop efficiently to reduce pipeline overhead. Simulation results in a 90nm technology show the proposed designs achieve 26% power reduction compared to other flip-flops, with no degradation in speed and comparable area.
This document summarizes an adaptive fuzzy logic power filter for nonlinear systems. It proposes using a Takagi-Sugeno fuzzy logic controller (FLC) to control a three-phase shunt active power filter (SAPF) to compensate for harmonic distortion and power quality issues caused by nonlinear loads. The FLC generates reference compensation currents and maintains the SAPF DC capacitor voltage. It is compared to a conventional PI controller, with the FLC showing better robustness to load and system parameter changes. The document describes the instantaneous reactive power theory used to estimate compensation currents, the design of the Takagi-Sugeno FLC, and an adaptive hysteresis current control method to generate switching signals for the SAPF
Quantitative Modeling and Simulation of Single-Electron TransistorIRJET Journal
This document discusses quantitative modeling and simulation of the single-electron transistor (SET) using MATLAB Simulink. The SET is a nano-scaled transistor that operates using quantum tunneling of single electrons. The document describes the basic theory of quantum tunneling and Coulomb blockade in SETs. It then discusses modeling the SET using a master equation approach and simulating its DC characteristics such as current oscillations. Parameters like junction capacitance, gate capacitance, and temperature are varied to analyze their effect on SET characteristics.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
A modified Cuk DC-DC converter for DC microgrid systemsTELKOMNIKA JOURNAL
A new efficient step-updirect current-direct current (DC-DC) power converter that is suitable for DC microgrid systems is proposed in this paper. The proposed step-up DC-DC converter is derived from the conventional Cuk DC-DC power converter. Output voltage analysis that is useful to predict the conduction losses is presented. It is shown that the proposed step-up DC-DC converter is more efficient than the conventional DC-DC boost power converter. Current ripple analysis that is useful to determine the required inductors and capacitors is also presented. Experimental results are included to show the validity of the proposed step-up DC-DC power converter.
An Efficient Photo Voltaic System for Onboard Ship ApplicationsIJERA Editor
In this paper a high efficient photovoltaic system is proposed for onboard ship applications which convert the
lower voltage obtained from solar modules to higher voltage required by the ship service loads. In a typical
photovoltaic system only step-up /boost converter is used due to which the converter has to operate in extreme
duty ratio, resulting in increase of switching losses and thus decreasing the overall efficiency. But in this paper
the conventional boost converter is used with interleaved inductors and capacitors. The poposed system stores
the energy in inductors and thus reduces the stress in the switches (Without allowing the total voltage to appear
across the switch). The simulation is designed using MATLAB/Simulink with an Input voltage of 40-V to
achieve a output voltage of 300-380 V. The developed simulation results are compared for output powers of
500W and 1kW
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design and Analysis of Sequential Elements for Low Power Clocking System with...IJERA Editor
This document summarizes techniques for designing sequential elements for low power clocking systems. It describes conditional capture flip-flops, conditional discharge flip-flops, conditional data mapping flip-flops, and a proposed clock pair shared flip-flop design. Simulation results show the clock pair shared flip-flop uses the fewest clocked transistors and achieves a 12.84% power savings over other designs. The document also proposes applying dual sleep and sleepy stack techniques to existing flip-flop designs to reduce static power consumption from leakage currents.
Performance analysis of multiple energy storage element resonant power conver...asokan2k7
This document presents a performance analysis of a Multiple Energy Storage Element Resonant Power Converter with an LCLC configuration. It begins with an abstract summarizing the study of a proposed open loop LCLC converter. It then provides background on resonant converters and multiple energy storage element converters. The document establishes a state-space model and equations for the proposed LCLC converter. Finally, it presents simulation results demonstrating zero voltage switching, zero current switching, and steady-state output voltage and current waveforms for validation of the converter's operation.
1) The document discusses power flow analysis of a three bus power system using circuit theory concepts. It introduces notation for generation (q) and load (x) at each bus and derives an equation relating power flow between two buses to the generation and loads.
2) It models the system as an electric circuit with current sources representing generation (q) and loads (x) at each node. Through techniques like current division and superposition, the document derives the same power flow equation relating the flow between two buses to the differences in generation and loads at those buses.
3) It introduces the concept of "Ohm's law for real power flow" which relates the real power flow on a line to the difference in voltage
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
This document describes an asynchronous fine-grain power gated logic (AFPL) circuit for reducing power dissipation in asynchronous circuits. Each stage of the AFPL circuit contains an efficient charge recovery logic (ECRL) gate to perform logic functions and a handshake controller. The handshake controller provides power to the ECRL gate and handles handshaking between pipeline stages. A partial charge reuse mechanism can be integrated to reuse charge from one ECRL gate to power another, reducing energy. The AFPL circuit uses a novel C-element design called a Sutherland pull-up pull-down to allow ECRL gates to enter sleep mode earlier. Simulation results show the AFPL circuit achieves significant power savings compared to
This document presents a study of loosely coupled coils for wireless power transfer. It begins by introducing the concept of using magnetically coupled coils for nonradiative wireless power transfer. It then presents a conceptual wireless power transfer system and a tuning method for transferring a predetermined amount of power at maximum efficiency. Equations are derived for calculating inductance, resistance, coupling coefficient, power transfer capability, and efficiency. The performance of the proposed system is evaluated and verified using known experimental results and circuit simulations. Key aspects of the study include developing explicit design equations for tuning the wireless power transfer system to achieve a target power level with optimal efficiency.
The document discusses the Fast Decoupled Load Flow (FDLF) method for solving load flow problems. FDLF is based on the Newton-Raphson method but further simplifies the load flow equations by assuming that active power changes are more sensitive to voltage angle changes and reactive power changes are more sensitive to voltage magnitude changes. This allows the Jacobian matrix to be separated into two square submatrices related to voltage angle and magnitude. FDLF requires fewer iterations than Newton-Raphson, has higher reliability, and is faster and uses less storage. The method is physically justifiable and can be used in optimization studies involving multiple load flow solutions.
An Active Input Current Waveshaping with Zero Switching Losses for Three-Phas...IDES Editor
(1) The document presents an active switching network for a three-phase AC to DC boost converter that achieves zero switching losses while maintaining unity input power factor.
(2) The network uses capacitors and diodes to maintain zero voltage across the switches during turn-off, limiting current rise during turn-on.
(3) The network allows the boost converter to directly control the DC bus voltage by varying the duty cycle at a constant switching frequency, improving efficiency.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayannazrulanuar
The document summarizes a paper on Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL). It introduces 2PASCL, which uses adiabatic switching to reduce power dissipation. It describes the principle and analysis of 2PASCL, presents application circuits including a 4-bit adder and 4x4-bit multiplier, and discusses the LSI implementation of a 4x4-bit 2PASCL multiplier chip in a 1.2um CMOS process. Simulation and measurement results show the 2PASCL circuits dissipate 35-77% less power compared to equivalent CMOS designs.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Design of High Speed Low Power 15-4 Compressor Using Complementary Energy Pat...CSCJournals
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high speed multiplication applications using single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The main advantage of this static adiabatic logic is the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits. The proposed Compressor uses bit sliced architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed Compressor is also centered around the design of a novel 5-3 Compressor that attempts to minimize the stage delays of a conventional 5-3 Compressor that is designed using single bit full adder and half adder architectures. Firstly, the performance characteristics of CEPAL 15-3 Compressor with 14 transistor and 10 transistor adder designs are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250 nm technology libraries. The results prove that CEPAL 14T 15-4 Compressor is 68.11% power efficient, 75.31% faster over its static CMOS counterpart.
This document presents a new dual dynamic node hybrid flip-flop (DDFF) and embedded logic module (DDFF-ELM) designed to reduce power consumption in VLSI circuits. The DDFF splits the dynamic node to separately drive the pull-up and pull-down transistors, eliminating large capacitance. The DDFF-ELM incorporates logic functions into the flip-flop efficiently to reduce pipeline overhead. Simulation results in a 90nm technology show the proposed designs achieve 26% power reduction compared to other flip-flops, with no degradation in speed and comparable area.
This document summarizes an adaptive fuzzy logic power filter for nonlinear systems. It proposes using a Takagi-Sugeno fuzzy logic controller (FLC) to control a three-phase shunt active power filter (SAPF) to compensate for harmonic distortion and power quality issues caused by nonlinear loads. The FLC generates reference compensation currents and maintains the SAPF DC capacitor voltage. It is compared to a conventional PI controller, with the FLC showing better robustness to load and system parameter changes. The document describes the instantaneous reactive power theory used to estimate compensation currents, the design of the Takagi-Sugeno FLC, and an adaptive hysteresis current control method to generate switching signals for the SAPF
Quantitative Modeling and Simulation of Single-Electron TransistorIRJET Journal
This document discusses quantitative modeling and simulation of the single-electron transistor (SET) using MATLAB Simulink. The SET is a nano-scaled transistor that operates using quantum tunneling of single electrons. The document describes the basic theory of quantum tunneling and Coulomb blockade in SETs. It then discusses modeling the SET using a master equation approach and simulating its DC characteristics such as current oscillations. Parameters like junction capacitance, gate capacitance, and temperature are varied to analyze their effect on SET characteristics.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
A modified Cuk DC-DC converter for DC microgrid systemsTELKOMNIKA JOURNAL
A new efficient step-updirect current-direct current (DC-DC) power converter that is suitable for DC microgrid systems is proposed in this paper. The proposed step-up DC-DC converter is derived from the conventional Cuk DC-DC power converter. Output voltage analysis that is useful to predict the conduction losses is presented. It is shown that the proposed step-up DC-DC converter is more efficient than the conventional DC-DC boost power converter. Current ripple analysis that is useful to determine the required inductors and capacitors is also presented. Experimental results are included to show the validity of the proposed step-up DC-DC power converter.
An Efficient Photo Voltaic System for Onboard Ship ApplicationsIJERA Editor
In this paper a high efficient photovoltaic system is proposed for onboard ship applications which convert the
lower voltage obtained from solar modules to higher voltage required by the ship service loads. In a typical
photovoltaic system only step-up /boost converter is used due to which the converter has to operate in extreme
duty ratio, resulting in increase of switching losses and thus decreasing the overall efficiency. But in this paper
the conventional boost converter is used with interleaved inductors and capacitors. The poposed system stores
the energy in inductors and thus reduces the stress in the switches (Without allowing the total voltage to appear
across the switch). The simulation is designed using MATLAB/Simulink with an Input voltage of 40-V to
achieve a output voltage of 300-380 V. The developed simulation results are compared for output powers of
500W and 1kW
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design and Analysis of Sequential Elements for Low Power Clocking System with...IJERA Editor
This document summarizes techniques for designing sequential elements for low power clocking systems. It describes conditional capture flip-flops, conditional discharge flip-flops, conditional data mapping flip-flops, and a proposed clock pair shared flip-flop design. Simulation results show the clock pair shared flip-flop uses the fewest clocked transistors and achieves a 12.84% power savings over other designs. The document also proposes applying dual sleep and sleepy stack techniques to existing flip-flop designs to reduce static power consumption from leakage currents.
Performance analysis of multiple energy storage element resonant power conver...asokan2k7
This document presents a performance analysis of a Multiple Energy Storage Element Resonant Power Converter with an LCLC configuration. It begins with an abstract summarizing the study of a proposed open loop LCLC converter. It then provides background on resonant converters and multiple energy storage element converters. The document establishes a state-space model and equations for the proposed LCLC converter. Finally, it presents simulation results demonstrating zero voltage switching, zero current switching, and steady-state output voltage and current waveforms for validation of the converter's operation.
1) The document discusses power flow analysis of a three bus power system using circuit theory concepts. It introduces notation for generation (q) and load (x) at each bus and derives an equation relating power flow between two buses to the generation and loads.
2) It models the system as an electric circuit with current sources representing generation (q) and loads (x) at each node. Through techniques like current division and superposition, the document derives the same power flow equation relating the flow between two buses to the differences in generation and loads at those buses.
3) It introduces the concept of "Ohm's law for real power flow" which relates the real power flow on a line to the difference in voltage
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
This document describes an asynchronous fine-grain power gated logic (AFPL) circuit for reducing power dissipation in asynchronous circuits. Each stage of the AFPL circuit contains an efficient charge recovery logic (ECRL) gate to perform logic functions and a handshake controller. The handshake controller provides power to the ECRL gate and handles handshaking between pipeline stages. A partial charge reuse mechanism can be integrated to reuse charge from one ECRL gate to power another, reducing energy. The AFPL circuit uses a novel C-element design called a Sutherland pull-up pull-down to allow ECRL gates to enter sleep mode earlier. Simulation results show the AFPL circuit achieves significant power savings compared to
This document presents a study of loosely coupled coils for wireless power transfer. It begins by introducing the concept of using magnetically coupled coils for nonradiative wireless power transfer. It then presents a conceptual wireless power transfer system and a tuning method for transferring a predetermined amount of power at maximum efficiency. Equations are derived for calculating inductance, resistance, coupling coefficient, power transfer capability, and efficiency. The performance of the proposed system is evaluated and verified using known experimental results and circuit simulations. Key aspects of the study include developing explicit design equations for tuning the wireless power transfer system to achieve a target power level with optimal efficiency.
The document discusses the Fast Decoupled Load Flow (FDLF) method for solving load flow problems. FDLF is based on the Newton-Raphson method but further simplifies the load flow equations by assuming that active power changes are more sensitive to voltage angle changes and reactive power changes are more sensitive to voltage magnitude changes. This allows the Jacobian matrix to be separated into two square submatrices related to voltage angle and magnitude. FDLF requires fewer iterations than Newton-Raphson, has higher reliability, and is faster and uses less storage. The method is physically justifiable and can be used in optimization studies involving multiple load flow solutions.
An Active Input Current Waveshaping with Zero Switching Losses for Three-Phas...IDES Editor
(1) The document presents an active switching network for a three-phase AC to DC boost converter that achieves zero switching losses while maintaining unity input power factor.
(2) The network uses capacitors and diodes to maintain zero voltage across the switches during turn-off, limiting current rise during turn-on.
(3) The network allows the boost converter to directly control the DC bus voltage by varying the duty cycle at a constant switching frequency, improving efficiency.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayannazrulanuar
The document summarizes a paper on Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL). It introduces 2PASCL, which uses adiabatic switching to reduce power dissipation. It describes the principle and analysis of 2PASCL, presents application circuits including a 4-bit adder and 4x4-bit multiplier, and discusses the LSI implementation of a 4x4-bit 2PASCL multiplier chip in a 1.2um CMOS process. Simulation and measurement results show the 2PASCL circuits dissipate 35-77% less power compared to equivalent CMOS designs.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Design of High Speed Low Power 15-4 Compressor Using Complementary Energy Pat...CSCJournals
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high speed multiplication applications using single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The main advantage of this static adiabatic logic is the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits. The proposed Compressor uses bit sliced architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed Compressor is also centered around the design of a novel 5-3 Compressor that attempts to minimize the stage delays of a conventional 5-3 Compressor that is designed using single bit full adder and half adder architectures. Firstly, the performance characteristics of CEPAL 15-3 Compressor with 14 transistor and 10 transistor adder designs are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250 nm technology libraries. The results prove that CEPAL 14T 15-4 Compressor is 68.11% power efficient, 75.31% faster over its static CMOS counterpart.
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
The main goal of this paper to produce new low power solutions for very large scale
integration(VLSI).The main focus of this research on the power consumption, which is showing an
ever-increasing growth with scaling down of the technologies. The full adder is the most important
component of any digital system applications. To limit the power dissipation, this full adder is
designed with adiabatic technique PFAL and it compare with partial adiabatic technique ECRL.
These analysis have done on TANNER simulator V 7 technology. The power is reduced up to 70-
80% as compared to other methods.
Design and Implementation of Single Phase AC-DC Buck-Boost Converter for Powe...IJPEDS-IAES
This paper discusses the Power Factor Correction (PFC) for single phase AC-DC Buck-Boost Converter (BBC) operated in Continuous Conduction Mode (CCM) using inductor average current mode control. The proposed control technique employs Proportional-Integral (PI) controller in the outer voltage loop and the Inductor Average Current Mode Control (IACMC) in the inner current loop for PFC BBC. The IACMC has advantages such as robustness when there are large variations in line voltage and output load. The PI controller is developed by using state space average model of BBC. The simulation of the proposed system with its control circuit is implemented in MatLab/Simulink. The simulation results show a nearly unity power factor can be attained and there is almost no change in power factor when the line frequency is at various ranges. Experimental results are provided to show its validity and feasibility.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
IRJET- Implementation of Low Power 32-Bit Carry-Look Ahead Adder using Ad...IRJET Journal
This document describes the design and implementation of a low power 32-bit carry look ahead adder using adiabatic efficient charge recovery logic (ECRL). ECRL is an adiabatic logic that allows for energy recovery, leading to lower power consumption than conventional CMOS logic. The authors designed inverters, AND, OR, and EX-OR gates as well as 4, 8, 16, and 32-bit carry look ahead adders using ECRL in a 45nm technology. Simulation results showed the ECRL implementations consumed less average power than equivalent static CMOS designs. For example, the 32-bit ECRL carry look ahead adder consumed 36.76μw on average
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
PERFORMANCE ANALYSIS OF MODIFIED QSERL CIRCUITVLSICS Design
The document summarizes the performance analysis of a modified quasi-static energy recovery logic (MQSERL) circuit. Some key points:
1) MQSERL aims to improve energy efficiency over previous quasi-static energy recovery logic (QSERL) circuits by reducing non-adiabatic losses. It replaces diodes with transistors to minimize voltage drop.
2) The circuit uses two complementary sinusoidal power clocks for evaluation and hold phases. During evaluation, the load capacitance is slowly charged or discharged via transistors.
3) Simulation results show the MQSERL inverter has 30% lower energy dissipation than CMOS and 20% lower than QSERL up to 20MHz and 20fF
Analysis and characterization of different high density on chip switched capa...Aalay Kapadia
Power converter is a key component in micro-scale energy harvesting systems. Micro-scale energy harvesting has become an increasingly viable and promising area for powering ultra-low power systems. Switched-capacitor (SC) power converters that use capacitors as energy storage elements offer much better power density than switched-inductor counterparts and are thus attractive in low-power area-constrained applications. Switched-capacitor (SC) converters have shown tremendous promise in this regard due to favorable device utilization and scaling trends, and the emergence of high-density silicon-compatible capacitor technologies. With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. This project first reviews various design techniques for implementing high density On-chip Switched-capacitor (SC) power converters and secondly suggests the best technique to solve aspects of power converter design: Area Density, Power Consumption & Efficiency.
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
1) The document proposes a novel design of flip flops and a 4-bit up counter using Quantum-Dot Cellular Automata (QCA) technology. QCA is an emerging nanotechnology that could overcome scaling limitations of CMOS.
2) In QCA, logic states are represented by the position of electrons in quantum dots rather than voltage as in CMOS. Basic logic gates like inverters and majority gates are constructed using QCA cells.
3) The document designs various flip flops like SR, JK, D, and T flip flops in QCA and uses them to build a 4-bit up counter. Power consumption is shown to be lower for the QCA designs compared to
Modelling of fuzzy logic controller for variable step mppt in photovoltaic sy...eSAT Journals
Abstract
The output power of photovoltaic electrical systems is highly dynamic and non-linear in nature. In order to extract maximum power
from such systems, maximum power point tracking (MPPT) technique is required. MPPT techniques with variable step-size of
perturbation track the maximum power point (MPP) with more efficiency. In this paper, a model of a fuzzy logic controller (FLC) for
determining the step-size of perturbation in duty-cycle of a photovoltaic electrical system to track MPP is presented. The model is
simulated in MATLAB/Simulink®.
Keywords: Maximum power point tracking, perturb and observe, boost converter, fuzzy logic control, membership
function, crisp universe, centre of area, pulse width modulation
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
A Self-Balancing Switched Capacitor Multilevel Inverter Structure with Six-fo...IRJET Journal
This document describes a novel self-balancing switched capacitor multilevel inverter structure that can generate 13 voltage levels from a single DC supply using 3 capacitors and 14 switches. Key features include its ability to automatically balance capacitor voltages through series and parallel charging and discharging, and its reduction in maximum blocking voltage stress across switches compared to similar topologies. The document outlines the circuit configuration, operating principle with 13 states, capacitor sizing analysis, and modulation scheme. Simulation results validate the performance and viability of the proposed topology, which is well-suited for renewable energy applications due to its reduced switching stresses.
Similar to Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit (20)
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Neural network optimizer of proportional-integral-differential controller par...IJECEIAES
Wide application of proportional-integral-differential (PID)-regulator in industry requires constant improvement of methods of its parameters adjustment. The paper deals with the issues of optimization of PID-regulator parameters with the use of neural network technology methods. A methodology for choosing the architecture (structure) of neural network optimizer is proposed, which consists in determining the number of layers, the number of neurons in each layer, as well as the form and type of activation function. Algorithms of neural network training based on the application of the method of minimizing the mismatch between the regulated value and the target value are developed. The method of back propagation of gradients is proposed to select the optimal training rate of neurons of the neural network. The neural network optimizer, which is a superstructure of the linear PID controller, allows increasing the regulation accuracy from 0.23 to 0.09, thus reducing the power consumption from 65% to 53%. The results of the conducted experiments allow us to conclude that the created neural superstructure may well become a prototype of an automatic voltage regulator (AVR)-type industrial controller for tuning the parameters of the PID controller.
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
simplified modulation technique paves the way for more straightforward and
efficient control of multilevel inverters, enabling their widespread adoption and
integration into modern power electronic systems. Through the amalgamation of
sinusoidal pulse width modulation (SPWM) with a high-frequency square wave
pulse, this controlling technique attains energy equilibrium across the coupling
capacitor. The modulation scheme incorporates a simplified switching pattern
and a decreased count of voltage references, thereby simplifying the control
algorithm.
A review on features and methods of potential fishing zoneIJECEIAES
This review focuses on the importance of identifying potential fishing zones in seawater for sustainable fishing practices. It explores features like sea surface temperature (SST) and sea surface height (SSH), along with classification methods such as classifiers. The features like SST, SSH, and different classifiers used to classify the data, have been figured out in this review study. This study underscores the importance of examining potential fishing zones using advanced analytical techniques. It thoroughly explores the methodologies employed by researchers, covering both past and current approaches. The examination centers on data characteristics and the application of classification algorithms for classification of potential fishing zones. Furthermore, the prediction of potential fishing zones relies significantly on the effectiveness of classification algorithms. Previous research has assessed the performance of models like support vector machines, naïve Bayes, and artificial neural networks (ANN). In the previous result, the results of support vector machine (SVM) were 97.6% more accurate than naive Bayes's 94.2% to classify test data for fisheries classification. By considering the recent works in this area, several recommendations for future works are presented to further improve the performance of the potential fishing zone models, which is important to the fisheries community.
Electrical signal interference minimization using appropriate core material f...IJECEIAES
As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Bibliometric analysis highlighting the role of women in addressing climate ch...IJECEIAES
Fossil fuel consumption increased quickly, contributing to climate change
that is evident in unusual flooding and draughts, and global warming. Over
the past ten years, women's involvement in society has grown dramatically,
and they succeeded in playing a noticeable role in reducing climate change.
A bibliometric analysis of data from the last ten years has been carried out to
examine the role of women in addressing the climate change. The analysis's
findings discussed the relevant to the sustainable development goals (SDGs),
particularly SDG 7 and SDG 13. The results considered contributions made
by women in the various sectors while taking geographic dispersion into
account. The bibliometric analysis delves into topics including women's
leadership in environmental groups, their involvement in policymaking, their
contributions to sustainable development projects, and the influence of
gender diversity on attempts to mitigate climate change. This study's results
highlight how women have influenced policies and actions related to climate
change, point out areas of research deficiency and recommendations on how
to increase role of the women in addressing the climate change and
achieving sustainability. To achieve more successful results, this initiative
aims to highlight the significance of gender equality and encourage
inclusivity in climate change decision-making processes.
Voltage and frequency control of microgrid in presence of micro-turbine inter...IJECEIAES
The active and reactive load changes have a significant impact on voltage
and frequency. In this paper, in order to stabilize the microgrid (MG) against
load variations in islanding mode, the active and reactive power of all
distributed generators (DGs), including energy storage (battery), diesel
generator, and micro-turbine, are controlled. The micro-turbine generator is
connected to MG through a three-phase to three-phase matrix converter, and
the droop control method is applied for controlling the voltage and
frequency of MG. In addition, a method is introduced for voltage and
frequency control of micro-turbines in the transition state from gridconnected mode to islanding mode. A novel switching strategy of the matrix
converter is used for converting the high-frequency output voltage of the
micro-turbine to the grid-side frequency of the utility system. Moreover,
using the switching strategy, the low-order harmonics in the output current
and voltage are not produced, and consequently, the size of the output filter
would be reduced. In fact, the suggested control strategy is load-independent
and has no frequency conversion restrictions. The proposed approach for
voltage and frequency regulation demonstrates exceptional performance and
favorable response across various load alteration scenarios. The suggested
strategy is examined in several scenarios in the MG test systems, and the
simulation results are addressed.
Enhancing battery system identification: nonlinear autoregressive modeling fo...IJECEIAES
Precisely characterizing Li-ion batteries is essential for optimizing their
performance, enhancing safety, and prolonging their lifespan across various
applications, such as electric vehicles and renewable energy systems. This
article introduces an innovative nonlinear methodology for system
identification of a Li-ion battery, employing a nonlinear autoregressive with
exogenous inputs (NARX) model. The proposed approach integrates the
benefits of nonlinear modeling with the adaptability of the NARX structure,
facilitating a more comprehensive representation of the intricate
electrochemical processes within the battery. Experimental data collected
from a Li-ion battery operating under diverse scenarios are employed to
validate the effectiveness of the proposed methodology. The identified
NARX model exhibits superior accuracy in predicting the battery's behavior
compared to traditional linear models. This study underscores the
importance of accounting for nonlinearities in battery modeling, providing
insights into the intricate relationships between state-of-charge, voltage, and
current under dynamic conditions.
Smart grid deployment: from a bibliometric analysis to a surveyIJECEIAES
Smart grids are one of the last decades' innovations in electrical energy.
They bring relevant advantages compared to the traditional grid and
significant interest from the research community. Assessing the field's
evolution is essential to propose guidelines for facing new and future smart
grid challenges. In addition, knowing the main technologies involved in the
deployment of smart grids (SGs) is important to highlight possible
shortcomings that can be mitigated by developing new tools. This paper
contributes to the research trends mentioned above by focusing on two
objectives. First, a bibliometric analysis is presented to give an overview of
the current research level about smart grid deployment. Second, a survey of
the main technological approaches used for smart grid implementation and
their contributions are highlighted. To that effect, we searched the Web of
Science (WoS), and the Scopus databases. We obtained 5,663 documents
from WoS and 7,215 from Scopus on smart grid implementation or
deployment. With the extraction limitation in the Scopus database, 5,872 of
the 7,215 documents were extracted using a multi-step process. These two
datasets have been analyzed using a bibliometric tool called bibliometrix.
The main outputs are presented with some recommendations for future
research.
Use of analytical hierarchy process for selecting and prioritizing islanding ...IJECEIAES
One of the problems that are associated to power systems is islanding
condition, which must be rapidly and properly detected to prevent any
negative consequences on the system's protection, stability, and security.
This paper offers a thorough overview of several islanding detection
strategies, which are divided into two categories: classic approaches,
including local and remote approaches, and modern techniques, including
techniques based on signal processing and computational intelligence.
Additionally, each approach is compared and assessed based on several
factors, including implementation costs, non-detected zones, declining
power quality, and response times using the analytical hierarchy process
(AHP). The multi-criteria decision-making analysis shows that the overall
weight of passive methods (24.7%), active methods (7.8%), hybrid methods
(5.6%), remote methods (14.5%), signal processing-based methods (26.6%),
and computational intelligent-based methods (20.8%) based on the
comparison of all criteria together. Thus, it can be seen from the total weight
that hybrid approaches are the least suitable to be chosen, while signal
processing-based methods are the most appropriate islanding detection
method to be selected and implemented in power system with respect to the
aforementioned factors. Using Expert Choice software, the proposed
hierarchy model is studied and examined.
Enhancing of single-stage grid-connected photovoltaic system using fuzzy logi...IJECEIAES
The power generated by photovoltaic (PV) systems is influenced by
environmental factors. This variability hampers the control and utilization of
solar cells' peak output. In this study, a single-stage grid-connected PV
system is designed to enhance power quality. Our approach employs fuzzy
logic in the direct power control (DPC) of a three-phase voltage source
inverter (VSI), enabling seamless integration of the PV connected to the
grid. Additionally, a fuzzy logic-based maximum power point tracking
(MPPT) controller is adopted, which outperforms traditional methods like
incremental conductance (INC) in enhancing solar cell efficiency and
minimizing the response time. Moreover, the inverter's real-time active and
reactive power is directly managed to achieve a unity power factor (UPF).
The system's performance is assessed through MATLAB/Simulink
implementation, showing marked improvement over conventional methods,
particularly in steady-state and varying weather conditions. For solar
irradiances of 500 and 1,000 W/m2
, the results show that the proposed
method reduces the total harmonic distortion (THD) of the injected current
to the grid by approximately 46% and 38% compared to conventional
methods, respectively. Furthermore, we compare the simulation results with
IEEE standards to evaluate the system's grid compatibility.
Enhancing photovoltaic system maximum power point tracking with fuzzy logic-b...IJECEIAES
Photovoltaic systems have emerged as a promising energy resource that
caters to the future needs of society, owing to their renewable, inexhaustible,
and cost-free nature. The power output of these systems relies on solar cell
radiation and temperature. In order to mitigate the dependence on
atmospheric conditions and enhance power tracking, a conventional
approach has been improved by integrating various methods. To optimize
the generation of electricity from solar systems, the maximum power point
tracking (MPPT) technique is employed. To overcome limitations such as
steady-state voltage oscillations and improve transient response, two
traditional MPPT methods, namely fuzzy logic controller (FLC) and perturb
and observe (P&O), have been modified. This research paper aims to
simulate and validate the step size of the proposed modified P&O and FLC
techniques within the MPPT algorithm using MATLAB/Simulink for
efficient power tracking in photovoltaic systems.
Adaptive synchronous sliding control for a robot manipulator based on neural ...IJECEIAES
Robot manipulators have become important equipment in production lines, medical fields, and transportation. Improving the quality of trajectory tracking for
robot hands is always an attractive topic in the research community. This is a
challenging problem because robot manipulators are complex nonlinear systems
and are often subject to fluctuations in loads and external disturbances. This
article proposes an adaptive synchronous sliding control scheme to improve trajectory tracking performance for a robot manipulator. The proposed controller
ensures that the positions of the joints track the desired trajectory, synchronize
the errors, and significantly reduces chattering. First, the synchronous tracking
errors and synchronous sliding surfaces are presented. Second, the synchronous
tracking error dynamics are determined. Third, a robust adaptive control law is
designed,the unknown components of the model are estimated online by the neural network, and the parameters of the switching elements are selected by fuzzy
logic. The built algorithm ensures that the tracking and approximation errors
are ultimately uniformly bounded (UUB). Finally, the effectiveness of the constructed algorithm is demonstrated through simulation and experimental results.
Simulation and experimental results show that the proposed controller is effective with small synchronous tracking errors, and the chattering phenomenon is
significantly reduced.
Remote field-programmable gate array laboratory for signal acquisition and de...IJECEIAES
A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embeddedsystem design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.
Detecting and resolving feature envy through automated machine learning and m...IJECEIAES
Efficiently identifying and resolving code smells enhances software project quality. This paper presents a novel solution, utilizing automated machine learning (AutoML) techniques, to detect code smells and apply move method refactoring. By evaluating code metrics before and after refactoring, we assessed its impact on coupling, complexity, and cohesion. Key contributions of this research include a unique dataset for code smell classification and the development of models using AutoGluon for optimal performance. Furthermore, the study identifies the top 20 influential features in classifying feature envy, a well-known code smell, stemming from excessive reliance on external classes. We also explored how move method refactoring addresses feature envy, revealing reduced coupling and complexity, and improved cohesion, ultimately enhancing code quality. In summary, this research offers an empirical, data-driven approach, integrating AutoML and move method refactoring to optimize software project quality. Insights gained shed light on the benefits of refactoring on code quality and the significance of specific features in detecting feature envy. Future research can expand to explore additional refactoring techniques and a broader range of code metrics, advancing software engineering practices and standards.
Smart monitoring technique for solar cell systems using internet of things ba...IJECEIAES
Rapidly and remotely monitoring and receiving the solar cell systems status parameters, solar irradiance, temperature, and humidity, are critical issues in enhancement their efficiency. Hence, in the present article an improved smart prototype of internet of things (IoT) technique based on embedded system through NodeMCU ESP8266 (ESP-12E) was carried out experimentally. Three different regions at Egypt; Luxor, Cairo, and El-Beheira cities were chosen to study their solar irradiance profile, temperature, and humidity by the proposed IoT system. The monitoring data of solar irradiance, temperature, and humidity were live visualized directly by Ubidots through hypertext transfer protocol (HTTP) protocol. The measured solar power radiation in Luxor, Cairo, and El-Beheira ranged between 216-1000, 245-958, and 187-692 W/m 2 respectively during the solar day. The accuracy and rapidity of obtaining monitoring results using the proposed IoT system made it a strong candidate for application in monitoring solar cell systems. On the other hand, the obtained solar power radiation results of the three considered regions strongly candidate Luxor and Cairo as suitable places to build up a solar cells system station rather than El-Beheira.
An efficient security framework for intrusion detection and prevention in int...IJECEIAES
Over the past few years, the internet of things (IoT) has advanced to connect billions of smart devices to improve quality of life. However, anomalies or malicious intrusions pose several security loopholes, leading to performance degradation and threat to data security in IoT operations. Thereby, IoT security systems must keep an eye on and restrict unwanted events from occurring in the IoT network. Recently, various technical solutions based on machine learning (ML) models have been derived towards identifying and restricting unwanted events in IoT. However, most ML-based approaches are prone to miss-classification due to inappropriate feature selection. Additionally, most ML approaches applied to intrusion detection and prevention consider supervised learning, which requires a large amount of labeled data to be trained. Consequently, such complex datasets are impossible to source in a large network like IoT. To address this problem, this proposed study introduces an efficient learning mechanism to strengthen the IoT security aspects. The proposed algorithm incorporates supervised and unsupervised approaches to improve the learning models for intrusion detection and mitigation. Compared with the related works, the experimental outcome shows that the model performs well in a benchmark dataset. It accomplishes an improved detection accuracy of approximately 99.21%.
Sri Guru Hargobind Ji - Bandi Chor Guru.pdfBalvir Singh
Sri Guru Hargobind Ji (19 June 1595 - 3 March 1644) is revered as the Sixth Nanak.
• On 25 May 1606 Guru Arjan nominated his son Sri Hargobind Ji as his successor. Shortly
afterwards, Guru Arjan was arrested, tortured and killed by order of the Mogul Emperor
Jahangir.
• Guru Hargobind's succession ceremony took place on 24 June 1606. He was barely
eleven years old when he became 6th Guru.
• As ordered by Guru Arjan Dev Ji, he put on two swords, one indicated his spiritual
authority (PIRI) and the other, his temporal authority (MIRI). He thus for the first time
initiated military tradition in the Sikh faith to resist religious persecution, protect
people’s freedom and independence to practice religion by choice. He transformed
Sikhs to be Saints and Soldier.
• He had a long tenure as Guru, lasting 37 years, 9 months and 3 days
This is an overview of my current metallic design and engineering knowledge base built up over my professional career and two MSc degrees : - MSc in Advanced Manufacturing Technology University of Portsmouth graduated 1st May 1998, and MSc in Aircraft Engineering Cranfield University graduated 8th June 2007.
An In-Depth Exploration of Natural Language Processing: Evolution, Applicatio...DharmaBanothu
Natural language processing (NLP) has
recently garnered significant interest for the
computational representation and analysis of human
language. Its applications span multiple domains such
as machine translation, email spam detection,
information extraction, summarization, healthcare,
and question answering. This paper first delineates
four phases by examining various levels of NLP and
components of Natural Language Generation,
followed by a review of the history and progression of
NLP. Subsequently, we delve into the current state of
the art by presenting diverse NLP applications,
contemporary trends, and challenges. Finally, we
discuss some available datasets, models, and
evaluation metrics in NLP.
Online train ticket booking system project.pdfKamal Acharya
Rail transport is one of the important modes of transport in India. Now a days we
see that there are railways that are present for the long as well as short distance
travelling which makes the life of the people easier. When compared to other
means of transport, a railway is the cheapest means of transport. The maintenance
of the railway database also plays a major role in the smooth running of this
system. The Online Train Ticket Management System will help in reserving the
tickets of the railways to travel from a particular source to the destination.
Covid Management System Project Report.pdfKamal Acharya
CoVID-19 sprang up in Wuhan China in November 2019 and was declared a pandemic by the in January 2020 World Health Organization (WHO). Like the Spanish flu of 1918 that claimed millions of lives, the COVID-19 has caused the demise of thousands with China, Italy, Spain, USA and India having the highest statistics on infection and mortality rates. Regardless of existing sophisticated technologies and medical science, the spread has continued to surge high. With this COVID-19 Management System, organizations can respond virtually to the COVID-19 pandemic and protect, educate and care for citizens in the community in a quick and effective manner. This comprehensive solution not only helps in containing the virus but also proactively empowers both citizens and care providers to minimize the spread of the virus through targeted strategies and education.
This is an overview of my career in Aircraft Design and Structures, which I am still trying to post on LinkedIn. Includes my BAE Systems Structural Test roles/ my BAE Systems key design roles and my current work on academic projects.
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energy recovery principle. it uses time varying voltage supply instead of constant supply [10] as that of used
in CMOS circuits. The varying supply voltage charge the circuit during specific phases and supplied charge
is recovered during discharging event. The equation for the energy dissipation for Adiabatic logic is given as
2L
L dd
RC
E C V
T
=
(2)
Where R is resistor in charging and discharging path, CL is the load capacitance, Vdd is supply voltage, T is
total time required for charging and discharging the node capacitance. By increasing the time T, energy can
be reduced. For various low power applications many adiabatic logic circuits with different clocking scheme
have been proposed and analyzed [8]-[9].
In this paper, we focused on Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit
[11] because of its lower switching activity. We proposed improved structure for two phase clocked
adiabatic static CMOS logic (2PASCL). power dissipation of the proposed 2PASCL is less compared to the
reported one. It utilizes two sinusoidal power clock which are 1800
phase shifted with each other.
The rest of this paper is organized as follows. Section 2 describes proposed and reported 2PASCL
structure. In section 3 we designed the half adder, full adder ,nand gate , 2*2 and 4*4 array multiplier using
proposed logic style .Its simulation results and power dissipation is shown. As proposed logic gives less
power dissipation, the comparative power dissipation is summarized in section 4. Section 5 includes the
conclusion.
2. PROPOSED AND REPORTED TWO PHASE CLOCKED ADIABATIC STATIC CMOS
LOGIC (2PASCL) CIRCUIT
2.1. Reported Two Phase Clocked Aadiabatic Static CMOS Logic (2PASCL)
Two phase clocked adiabatic static CMOS logic [12]-[14] utilizes the principle of adiabatic
switching in which power dissipation occurs through the threshold voltage and transistor resistance. Figure 1
shows the structure of 2PASCL. The circuit uses two sinusoidal power clock which are 1800
phase shifted to
each other nodes.
Figure 1. Structure of 2PASCL
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The operation is performed in two phases Evaluation and Hold phase. The charging path is provided
by transistor P1 and discharging path is provided by transistor P2 and N1, N2. The expression for energy
dissipation is given as
arg ( 1) arg ( 2) arg ( 1, 2)ch ing P Disch ing P Disch ing N NE E E E= + +
=
2
0.5 0.5 0.5 ( )L tp L clk tp L clkbar tn tnC V C V V C V V V+ + −
=
2
0.5 { ( ) }L tp clk tp clkbar tn tnC V V V V V V+ + −
Where CL is the load capacitance, Vtp and Vtn are the threshold voltages of PMOS and NMOS
transistor. Vclk and Vclkbar are sinusoidal supply voltages which are 1800
phase shifted with each other and
peak to peak voltage of 1.8v. Figure 2 shows waveform of 2PASCL inverter circuit. It gives output low when
input is high and it passes the clock signal for input logic at low. The proposed structure tries to keep the
output logic at high when input is low instead of passing the clock signal as in case of reported 2PASCL.
Figure 2. Simulation Waveform for 2PASCL Inverter
2.2. Proposed Two Phase Clocked Aadiabatic Static CMOS Logic (2PASCL)
The Proposed 2PASCL [15] structure is shown in Figure 3. The gate terminal of transistor N2 is
connected to CLK and gate terminal of P2 is connected to CLKBAR. The operation of the circuit is
performed in two phases i.e. Evaluation phase and Hold phase.
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Figure 3. Structure of proposed 2PASCL
Circuit operation:
1. Evaluation phase: In Evaluation phase CLK goes high and CLKBAR goes low. When P1 transistor is on
and output is at logic low then CL is charged through P1 transistor and output reaches at logic high. When
output is high, Output load capacitor discharges through transistor N1 and N2 causes the output at low
level.
2. Hold phase: In hold phase CLK goes low and CLKBAR goes high no transitions occur as both the
transistor P2 and N2 will be off. Due to the hold phase, dynamic switching is reduced and hence energy
dissipation is reduced.
The Expression for the energy dissipation is given as
arg ( 1) arg ( 1, 2)ch ing P Disch ing N NE E E= +
=
2
0.5 0.5 ( )L tp L clkbar tn tnC V C V V V+ −
=
2
0.5 { ( ) }L tp clkbar tn tnC V V V V+ −
Thus from the expression of energy dissipation itself it is clear that in the proposed structure energy
dissipation through transistor P2 will not occur as in the reported structure.
Figure 4 shows simulation waveform for proposed 2PASCL inverter at clock frequency of 100 Mhz
and input signal frequency at 50 MHz. The proposed Inverter circuit saves 40.74% power over reported
2PASCL and 88.71% power over conventional CMOS inverter at clock frequency of 100 MHz and input
signal frequency of 50 MHz.
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Figure 4. Simulation Waveform for proposed 2PASCL Inverter
3. MULTIPLIER STRUCTURE
First we designed the circuits which are required for multiplier structure such as NAND, half adder,
full adder using both the logic style.
3.1. Half Adder
The design of half Adder using NAND gate is shown in Figure 5. A and B are the inputs and sum
and carry are the output of Half Adder. The simulation waveform of half adder using proposed 2PASCL is
shown in Figure 7. The proposed Half Adder circuit saves 65.92% power over reported 2PASCL and 93.49%
power over conventional CMOS logic at clock frequency of 100MHz and input signal frequency of 50 MHz.
Thus proposed 2PASCL Half adder shows improvement of 13% power conventional CMOS logic compared
with reported 2PASCL.
Figure 5. Block diagram of Half Adder
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Figure 6. Design of Half Adder gate using Proposed 2PASCL
Figure 7. Simulation Waveform for proposed 2PASCL Half Adder
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3.2. Full adder
The design of Full Adder is shown in Figure 8. Two half adders with addition of an OR gate to
combine their carry output Full adder is designed. A, B and Cin are three inputs sum and carry are the output
of Full adder circuit. The proposed Full Adder circuit saves 78.35% power over reported 2PASCL and
88.63% power over conventional CMOS logic at clock frequency of 100MHz and input signal frequency of
50 MHz. Thus proposed 2PASCL Full Adder shows improvement of 41.15% power conventional CMOS
logic compared with reported 2PASCL.
Figure 8. Block diagram of Full Adder Figure 9. Design of Full Adder using Proposed
2PASCL
Figure 10. Simulation Waveform for proposed 2PASCL Full Adder
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3.3. 2*2 Array Proposed 2PASCL Multiplier
Multiplication is one of the basic arithmetic operation and multiplier is fundamental functional unit
in most of the processors. Multiplier can be Array or parallel multiplier [16]-[17]. Both the type of multiplier
possesses high execution speed but the array multiplier has regular structure and occupies less space
compared with parallel multiplier. Figure 11 structure of array multiplier using half adder and AND gate.
Multiplier is designed using proposed logic style shown in figure 12, reported logic and conventional
logic.for 2*2 array multiplier inputs are a0,a1 and b0,b1 and p0,p1,p2,p3 are the outputs. For the Input 1111,
output is 1001 which can be verified from the simulation results shown in Figure 13.
Figure 11. Block diagram of 2*2 Array Multiplier
Figure 12. Design of 2*2 Array Multiplier using Proposed 2PASCL
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Figure 13. Simulation Waveform for proposed 2PASCL 2*2 Array Multiplier
3.4. 4*4 Array Proposed 2PASCL Multiplier
As shown in Figure 14, the 4_4-bit array 2PASCL multiplier consists of 16 ANDs, six full adder
logic circuits, and four half adder logic circuits. This 4*4 bit array multiplier [18] is designed using three
logic style i.e. CMOS logic, 2PASCL logic and Proposed 2PASCL logic. The proposed circuit
implementation is shown in Figure 15 and Figure 16 demonstrates the simulation result of array multiplier.
At the output load capacitance varying from 0.01pF to 0.1pF is set for p0 to p7. The proper working of the
circuit can be demonstrated from simulation result shown in Figure 16, however signal glitches will ocuur at
p4. The circuit consists of same transistor size and W/L ratio 180nm/180nm i.e. 1.the supply voltage is 1.8v.
and two sinusoidal clock signals are used which are 1800
phase shifted with each other.
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Figure 14. Block diagram of 4*4 Array Multiplier
Figure 15. Design of 4*4 Array Multiplier using Proposed 2PASCL
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Figure 16. Simulation Waveform for proposed 2PASCL 4*4 Array Multiplier
The proposed 2PASCL 4*4 bit array multiplier gives 32.88% power reduction compared to report
2PASCL multiplier and 82.02% reduction compared to conventional CMOS logic at clock frequency of
100MHz and input signal frequency of 50 MHz. Thus proposed multiplier shows improvement of 8.81%
over conventional CMOS logic compared with reported 2PASCL.
The proposed 4×4-bit array 2PASCL multiplier only shows a good logic functionality of up to 200
MHz transition frequency. We observe that for transition frequency of more than 200 MHz some signal
degradations will occur. This is due to the charging time T which is much slower than conventional CMOS.
T is also proportional to RCL i.e. the longer the path, the larger T is needed. These input frequencies are
adequate for the applications such as low power digital devices operated at low frequencies, such as radio-
frequency identifications (RFIDs), smart cards, and sensors.
4. RESULT AND ANALYSIS
The comparative power analysis has been done for the half adder, full adder, 2*2 bit array multiplier
and 4*4 bit array multiplier for the input frequency of 50MHz and clock signal frequency of 100MHz for the
signal transition from 1ns to 100ns. The Table 1 shows comparative power analysis of the circuits
implemented using the three logic style i.e. CMOS logic, 2PASCL logic and proposed 2PASCL logic and its
graphical analysis is shown in Figure 17.
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Table 1. Comparative Power Analysis
Figure 17. Comparative power analysis at clock frequency of 100MHz
5. CONCLUSION
Thus we designed and simulated a 4×4-bit array multiplier using three logic styles. The proposed
logic designs are compared with the reported one and conventional CMOS logic style. The proposed
2PASCL 2*2 bit multiplier is 80.53% and 97.67% power efficient over reported 2PASCL multiplier and
CMOS multiplier. The reported 2*2 PASCL multiplier is 88.04% power efficient compared to CMOS
multiplier. Thus the proposed structure has achieved efficiency of 9.63%. The proposed 2PASCL 4*4 bit
multiplier is 32.88% and 82.02% power efficient over reported 2PASCL multiplier and CMOS multiplier.
The reported 4*4 PASCL multiplier is 73.21% power efficient compared to CMOS logic multiplier. Thus the
proposed structure has achieved efficiency of 8.99%. Thus power consumption in the 2PASCL multiplier is
considerably less than that in a CMOS. We believe that the proposed adiabatic logic circuit is advantageous
for ultra low energy computing applications. As for our future work, we will further evaluate the cause of the
signal glitches in 2PASCL.
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[1] A. Bellaouar and M. Elmasry, “Low-Power Digital VLSI Design: Circuit and Systems,” Norwell, MA, Kluwer,
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(IJECE), vol/issue: 7(5), pp. 2468-2473, 2017.
[8] W. C. Athas, et al., “Low-power digital systems based on adiabatic-switching principles,” IEEE Trans. Very Large
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0
50
100
150
200
250
300
350
400
450
Power dissipation(uW)
CMOS
Power dissipation(uW)
Reported 2PASCL
Power dissipation(uW)
Proposed 2PASCL
PowerDissipated
Device Power dissipation(uW)
CMOS 2PASCL[14] Proposed 2PASCL
AND Gate 0.849 0.409 0.134
HALF ADDER 63.5 12.12 4.13
FULL ADDER 72.59 38.12 8.25
2*2 MULTIPLIER 45.32 5.416 1.054
4*4 MULTIPLIER 381.66 102.22 68.60
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[9] L. Svensson, “Adiabatic switching,” in A. Chrakasan and R. Brodersen, “Low Power Digital CMOS Design,”
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BIOGRAPHIES OF AUTHORS
Minal Keote was born in India in 1982. She did B.E. in 2004 and M.Tech in 2009 in
Electronics Eng from Yeshwantrao Chavan College of Engineering, Nagpur, India. She is
currently perusing Ph.D from Rashtrasant Tukdoji Maharaj Nagpur university in YCCE as
research Centre .Her area of research interests is low power VLSI circuits. Minal keote is
currently working as Assistant Professor in Yeshwantrao Chavan College of Engineering
since 2010. She has published total 10 research papers in international journals and
international conference paper till date.
Dr. P.T. Karule was born in India and persued his B. E. (Electronics and Power) from Govt.
College of Engineering, Amravati. in 1986, M.Tech. (Electronics Engineering) from VNIT,
Nagpur in 1992 and Ph.D. in the area of Medical Image Processing & Neural Network from
Amravati University in 2010. He has 25 years of teaching experience. His area of expertise
is microprocessors and embedded system At present he is Professor in Department of
Electronics Engineering of YCCE and also looking after administrative work of autonomous
YCCE as Registrar. Earlier he was Head of Department of ECE, YCCE; during his tenure
he started the popular activity of workshop series for students on current technologies with
hands-on practice in summer & winter vacation to enhance the employability. He had also
worked as Dean Industry Institute Interaction; YCCE He had Published 51 research papers
in various international journals & international and national conferences. He received Best
Paper Award at PSG college of Engineering.