Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
This document discusses optimizing the gate-level area of digit-serial finite impulse response (FIR) filter designs using multiple constant multiplication (MCM) blocks. It introduces the problem of designing a digit-serial MCM operation with minimal area and presents algorithms to formalize the area optimization problem. Results show the proposed algorithms and digit-serial MCM architectures efficiently design digit-serial MCM operations and FIR filters with reduced area compared to existing approaches.
This document summarizes a research paper on designing low power digit serial finite impulse response (FIR) filters using multiple constant multiplication (MCM) techniques. It proposes an architecture that optimizes the area of digit serial MCM operations at the gate level by considering the implementation costs of digit serial addition, subtraction and shift operations. An algorithm is presented to design digit serial FIR filters under a shift-adds architecture to reduce area compared to designs using generic digit serial multipliers. Experimental results show the technique leads to lower complexity digit serial MCM designs.
In the VLSI physical design, Floorplanning is the very crucial step as it optimizes the chip. The goal of
floorplanning is to find a floorplan such that no module overlaps with other, optimize the interconnection between
the modules, optimize the area of the floorplan and minimize the dead space. In this Paper, Simulated Annealing (SA)
algorithm has been employed to shrink dead space to optimize area and interconnect of VLSI floorplanning problem.
Sequence pair representation is employed to perturb the solution. The outcomes received after the application of SA
on different benchmark files are compared with the outcomes of different algorithms on same benchmark files and
the comparison suggests that the SA gives the better result. SA is effective and promising in VLSI floorplan design.
Matlab simulation results show that our approach can give better results and satisfy the fixed-outline and nonoverlapping
constraints while optimizing circuit performance.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
1. The document presents a design for a modified Booth recoder using a fused add-multiply (FAM) operator to implement digital signal processing applications more efficiently.
2. It proposes a new recoding technique to decrease the critical path delay and reduce area and power consumption of the FAM unit compared to existing recoding schemes.
3. The technique is also applied to the implementation of finite impulse response (FIR) filters to further optimize hardware usage and achieve faithfully rounded outputs within tight area and power constraints for mobile applications.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
Towards Efficient Modular Adders based on Reversible CircuitsIJSRED
This document discusses the design of efficient modular adders based on reversible circuits. It proposes combining residue number systems (RNS) with reversible computing to achieve an ultra-efficient computing paradigm for emerging applications. RNS allows for parallel and carry-free arithmetic, which is well-suited to take advantage of the properties of reversible circuits. However, existing RNS architectures were designed for ASIC implementation and need to be adapted for reversible circuits. Modular addition is a key operation in RNS since addition is used in forward and reverse conversion as well as other operations. The document presents implementations of modular adders using reversible gates like Feynman, Peres and HNG gates. Experimental results show modulo adders can be designed using reversible
This document discusses optimizing the gate-level area of digit-serial finite impulse response (FIR) filter designs using multiple constant multiplication (MCM) blocks. It introduces the problem of designing a digit-serial MCM operation with minimal area and presents algorithms to formalize the area optimization problem. Results show the proposed algorithms and digit-serial MCM architectures efficiently design digit-serial MCM operations and FIR filters with reduced area compared to existing approaches.
This document summarizes a research paper on designing low power digit serial finite impulse response (FIR) filters using multiple constant multiplication (MCM) techniques. It proposes an architecture that optimizes the area of digit serial MCM operations at the gate level by considering the implementation costs of digit serial addition, subtraction and shift operations. An algorithm is presented to design digit serial FIR filters under a shift-adds architecture to reduce area compared to designs using generic digit serial multipliers. Experimental results show the technique leads to lower complexity digit serial MCM designs.
In the VLSI physical design, Floorplanning is the very crucial step as it optimizes the chip. The goal of
floorplanning is to find a floorplan such that no module overlaps with other, optimize the interconnection between
the modules, optimize the area of the floorplan and minimize the dead space. In this Paper, Simulated Annealing (SA)
algorithm has been employed to shrink dead space to optimize area and interconnect of VLSI floorplanning problem.
Sequence pair representation is employed to perturb the solution. The outcomes received after the application of SA
on different benchmark files are compared with the outcomes of different algorithms on same benchmark files and
the comparison suggests that the SA gives the better result. SA is effective and promising in VLSI floorplan design.
Matlab simulation results show that our approach can give better results and satisfy the fixed-outline and nonoverlapping
constraints while optimizing circuit performance.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
1. The document presents a design for a modified Booth recoder using a fused add-multiply (FAM) operator to implement digital signal processing applications more efficiently.
2. It proposes a new recoding technique to decrease the critical path delay and reduce area and power consumption of the FAM unit compared to existing recoding schemes.
3. The technique is also applied to the implementation of finite impulse response (FIR) filters to further optimize hardware usage and achieve faithfully rounded outputs within tight area and power constraints for mobile applications.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
Towards Efficient Modular Adders based on Reversible CircuitsIJSRED
This document discusses the design of efficient modular adders based on reversible circuits. It proposes combining residue number systems (RNS) with reversible computing to achieve an ultra-efficient computing paradigm for emerging applications. RNS allows for parallel and carry-free arithmetic, which is well-suited to take advantage of the properties of reversible circuits. However, existing RNS architectures were designed for ASIC implementation and need to be adapted for reversible circuits. Modular addition is a key operation in RNS since addition is used in forward and reverse conversion as well as other operations. The document presents implementations of modular adders using reversible gates like Feynman, Peres and HNG gates. Experimental results show modulo adders can be designed using reversible
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
This document analyzes various multiple constant multiplication (MCM) algorithms for implementing reconfigurable root raised cosine (RRC) finite impulse response (FIR) filters. It compares digit based recoding, canonic sign digit (CSD), common subexpression elimination (CSE), and binary common subexpression elimination (BCSE) algorithms in terms of area, power, and speed. The results show that the BCSE algorithm provides the best performance, reducing area by up to 11.7% and power consumption compared to the other methods. The BCSE technique reuses common binary bit patterns within filter coefficients to optimize constant multiplications.
IRJET- Design and Implementation of Combinational Circuits using Reversible G...IRJET Journal
This document discusses the design and implementation of combinational circuits using reversible gates to reduce power consumption. It begins with an introduction to reversible logic and discusses how reversible gates can be used to design logic circuits without information loss and zero energy dissipation. Several reversible gates are described including NOT, Feynman, Toffoli and Fredkin gates. The document then presents the design of a 2x4 decoder and 4x16 decoder using reversible gates like Peres, TR and CNOT gates. Simulation results demonstrating the outputs of the decoders are shown. Finally, a comparative study of reversible decoders in terms of quantum cost and garbage outputs is discussed. The conclusion states that reversible logic allows minimizing fan-out limitations and quantum cost in combinational
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
This document summarizes an academic paper that proposes optimizing elliptic curve cryptography (ECC) through application-specific instruction set processor (ASIP) design. It applies pipelining techniques to the data path and uses complex instructions to reduce latency and the number of instructions needed for point multiplication. The paper describes applying different levels of pipelining to explore performance and find an optimal pipeline depth. It also develops a new combined algorithm to perform point doubling and addition using the specialized instructions. An FPGA implementation over GF(2163) is presented and shown to outperform previous work.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODELVLSICS Design
This document summarizes a research paper on implementing a low power design methodology for recursive encoders and decoders. It discusses how recursive coding can achieve better error correction performance at low signal-to-noise ratios compared to other codes. It then describes the design of a recursive decoder that uses the log-MAP algorithm to minimize power consumption. The decoder uses five main computational steps - branch metric calculation, forward metric computation, backward metric computation, log-likelihood ratio calculation, and extrinsic information calculation. It also compares the implementation of four-state and eight-state recursive encoders. The goal of the design is to optimize the power and area of recursive encoders and decoders.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
This document describes the design of a finite impulse response (FIR) filter using a modified Montgomery multiplier with pipelining. It first provides background on Montgomery multiplication and pipelining techniques. It then describes implementing a 32-bit Montgomery multiplier with pipelining and analyzing its performance. An 8-tap FIR filter is designed using this Montgomery multiplier architecture. Simulation and synthesis results show the area and timing of the Montgomery multiplier and FIR filter. The proposed method achieves better performance than existing methods.
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
IRJET- Review Paper on Radix-2 DIT Fast Fourier Transform using Reversible GateIRJET Journal
1) The document discusses a review paper on implementing a radix-2 Decimation-In-Time (DIT) Fast Fourier Transform (FFT) using reversible DKG gates.
2) The proposed design uses a 4x4 reversible DKG gate that functions as both an adder and subtractor.
3) The design is synthesized using Xilinx ISE software and simulated using VHDL test benches to evaluate performance.
37 9144 new technique based peasant multiplication (edit lafi)IAESIJEECS
The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.
This document summarizes a research paper about realizing complementary Boolean functions in a power-efficient manner using static CMOS logic. The paper proposes a method that algebraically factors Reed-Muller forms to reduce gate count and power consumption. Simulation results show the proposed method achieves on average 26.79% lower power consumption compared to other factored Reed-Muller forms, with reductions of 39.66% in gate count and 12.98% in input literals. However, this approach may decrease the testability of the resulting circuits.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document discusses a study that uses the ke-REM (ke-Rule Extraction Method) classifier to predict promoter regions in DNA sequences. The study evaluates the performance of ke-REM compared to existing promoter prediction techniques. ke-REM constructs rules based on attribute-value pairs from a dataset of 106 E. coli DNA sequences, each containing 57 nucleotides. The results show that ke-REM competes well with existing methods for identifying promoter regions in DNA.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document discusses the emerging health threats posed by electronic waste (e-waste). It begins by defining e-waste and noting that it makes up 2.7-3% of total waste but contains many toxic and hazardous elements. The main constituents of e-waste are discussed, including heavy metals like lead, mercury, and cadmium which can cause health effects when exposed. India's annual e-waste generation is estimated at 400,000 tons and is growing rapidly. While formal recycling systems exist, most e-waste in developing countries is handled by the informal sector without proper health and safety practices, exposing workers and local communities to the toxic materials. Proper regulations and disposal facilities are needed to address this important environmental and public
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
This document analyzes various multiple constant multiplication (MCM) algorithms for implementing reconfigurable root raised cosine (RRC) finite impulse response (FIR) filters. It compares digit based recoding, canonic sign digit (CSD), common subexpression elimination (CSE), and binary common subexpression elimination (BCSE) algorithms in terms of area, power, and speed. The results show that the BCSE algorithm provides the best performance, reducing area by up to 11.7% and power consumption compared to the other methods. The BCSE technique reuses common binary bit patterns within filter coefficients to optimize constant multiplications.
IRJET- Design and Implementation of Combinational Circuits using Reversible G...IRJET Journal
This document discusses the design and implementation of combinational circuits using reversible gates to reduce power consumption. It begins with an introduction to reversible logic and discusses how reversible gates can be used to design logic circuits without information loss and zero energy dissipation. Several reversible gates are described including NOT, Feynman, Toffoli and Fredkin gates. The document then presents the design of a 2x4 decoder and 4x16 decoder using reversible gates like Peres, TR and CNOT gates. Simulation results demonstrating the outputs of the decoders are shown. Finally, a comparative study of reversible decoders in terms of quantum cost and garbage outputs is discussed. The conclusion states that reversible logic allows minimizing fan-out limitations and quantum cost in combinational
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
This document summarizes an academic paper that proposes optimizing elliptic curve cryptography (ECC) through application-specific instruction set processor (ASIP) design. It applies pipelining techniques to the data path and uses complex instructions to reduce latency and the number of instructions needed for point multiplication. The paper describes applying different levels of pipelining to explore performance and find an optimal pipeline depth. It also develops a new combined algorithm to perform point doubling and addition using the specialized instructions. An FPGA implementation over GF(2163) is presented and shown to outperform previous work.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODELVLSICS Design
This document summarizes a research paper on implementing a low power design methodology for recursive encoders and decoders. It discusses how recursive coding can achieve better error correction performance at low signal-to-noise ratios compared to other codes. It then describes the design of a recursive decoder that uses the log-MAP algorithm to minimize power consumption. The decoder uses five main computational steps - branch metric calculation, forward metric computation, backward metric computation, log-likelihood ratio calculation, and extrinsic information calculation. It also compares the implementation of four-state and eight-state recursive encoders. The goal of the design is to optimize the power and area of recursive encoders and decoders.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
This document describes the design of a finite impulse response (FIR) filter using a modified Montgomery multiplier with pipelining. It first provides background on Montgomery multiplication and pipelining techniques. It then describes implementing a 32-bit Montgomery multiplier with pipelining and analyzing its performance. An 8-tap FIR filter is designed using this Montgomery multiplier architecture. Simulation and synthesis results show the area and timing of the Montgomery multiplier and FIR filter. The proposed method achieves better performance than existing methods.
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
IRJET- Review Paper on Radix-2 DIT Fast Fourier Transform using Reversible GateIRJET Journal
1) The document discusses a review paper on implementing a radix-2 Decimation-In-Time (DIT) Fast Fourier Transform (FFT) using reversible DKG gates.
2) The proposed design uses a 4x4 reversible DKG gate that functions as both an adder and subtractor.
3) The design is synthesized using Xilinx ISE software and simulated using VHDL test benches to evaluate performance.
37 9144 new technique based peasant multiplication (edit lafi)IAESIJEECS
The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.
This document summarizes a research paper about realizing complementary Boolean functions in a power-efficient manner using static CMOS logic. The paper proposes a method that algebraically factors Reed-Muller forms to reduce gate count and power consumption. Simulation results show the proposed method achieves on average 26.79% lower power consumption compared to other factored Reed-Muller forms, with reductions of 39.66% in gate count and 12.98% in input literals. However, this approach may decrease the testability of the resulting circuits.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document discusses a study that uses the ke-REM (ke-Rule Extraction Method) classifier to predict promoter regions in DNA sequences. The study evaluates the performance of ke-REM compared to existing promoter prediction techniques. ke-REM constructs rules based on attribute-value pairs from a dataset of 106 E. coli DNA sequences, each containing 57 nucleotides. The results show that ke-REM competes well with existing methods for identifying promoter regions in DNA.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document discusses the emerging health threats posed by electronic waste (e-waste). It begins by defining e-waste and noting that it makes up 2.7-3% of total waste but contains many toxic and hazardous elements. The main constituents of e-waste are discussed, including heavy metals like lead, mercury, and cadmium which can cause health effects when exposed. India's annual e-waste generation is estimated at 400,000 tons and is growing rapidly. While formal recycling systems exist, most e-waste in developing countries is handled by the informal sector without proper health and safety practices, exposing workers and local communities to the toxic materials. Proper regulations and disposal facilities are needed to address this important environmental and public
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
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This document summarizes an academic paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a design and implementation of an elliptic curve scalar multiplier on a field programmable gate array (FPGA) using the Karatsuba algorithm. It aims to reduce hardware complexity by using a polynomial basis representation of finite fields and projective coordinate representation of elliptic curves. Key mathematical concepts like finite fields, point addition, and point doubling that are important to elliptic curve cryptography are also discussed at a high level.
International Journal of Engineering Research and DevelopmentIJERD Editor
This document describes a proposed VLSI architecture for an optimized low power digit serial finite impulse response (FIR) filter using multiple constant multiplications (MCM). It introduces an algorithm to optimize the area of digit serial MCM operations at the gate level by considering implementation costs of digit serial addition, subtraction, and shift operations. The proposed filter architecture aims to reduce area and power compared to designs using generic digit serial multipliers through the use of MCM blocks optimized for area. Experimental results indicate the algorithm leads to lower complexity digit serial MCM designs.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
High Performance Binary to Gray Code Converter using Transmission GATE IJEEE
This document discusses the design and implementation of a binary to gray code converter using both conventional CMOS logic gates and transmission gates. It finds that a design using transmission gates improves power efficiency by 76.22% and reduces the effective area by 72.3% compared to a design using CMOS logic gates. The transmission gate implementation also reduces the number of transistors from 36 to 18. Layouts of the converter were created using both fully automatic and semi-custom design in Microwind3.1. Simulation results show that the transmission gate semi-custom layout has the lowest power at 10.7μW and smallest area at 47.5μm2, making it the most efficient implementation.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to
around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is
evaluated by comparing its performance with those of some approximate and correct multipliers using
different design parameters. In this proposed approach combined the conventional RoBA multiplier with
Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA
multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved
the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the
DSP
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to
around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is
evaluated by comparing its performance with those of some approximate and correct multipliers using
different design parameters. In this proposed approach combined the conventional RoBA multiplier with
Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA
multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved
the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the
DSP.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
This document discusses the implementation of a Radix-4 Booth multiplier using VHDL. It begins with an introduction to multipliers and their importance in digital circuits. It then provides background on Booth multiplication algorithms and related work that has been done to improve multiplier speed and efficiency. The methodology section describes the design of a configurable Booth multiplier that can detect the bit range of the operands and perform the multiplication accordingly in fewer cycles to reduce delay. Simulation results are provided to verify the operation of the Radix-4 Booth multiplier design for different input values.
IRJET- Design and Implementation of Combinational Circuits using Reversib...IRJET Journal
This document discusses the design and implementation of combinational circuits using reversible gates to reduce power consumption. It describes various reversible gates like NOT, Feynman, Toffoli, and Fredkin gates. Reversible decoders are designed using these gates to implement 2x4, 3x8, and 4x16 decoders with lower quantum costs and garbage outputs compared to traditional designs. The reversible decoder approach allows designing combinational circuits like adders and comparators with better performance. Simulation results demonstrate the working of the designed reversible decoders.
IRJET- FPGA Implementation of Efficient Muf Gate based MultipliersIRJET Journal
This document discusses the FPGA implementation of efficient multiplier circuits using reversible MUF gates. It begins with background on reversible logic and the benefits of reducing heat dissipation. A reversible MUF gate is proposed that can realize basic logic functions with unique input-output mappings. Array, systolic, and Wallace tree multipliers are designed using the MUF gate in place of conventional adders to reduce area and delay. Simulation results on Xilinx FPGA show the proposed multipliers require fewer gates and have lower delay compared to existing designs, indicating benefits for low power DSP applications.
This paper presents a compact design of Montgomery modular multiplier
(MMM). MMM serves as a building block commonly required in security
protocols relying on public key encryption. The proposed design is intended
for hardware applications of lightweight cryptographic modules that is utilized
for the system on chip (SoC) and internet of things (IoT) devices. The proposed
design is an enhancement of the original MMM without any multiplication or
subtraction processes. The main target of the new modification is enhancing
the performance and reducing the area of the MMM hardware module. The
operands and internal variables of the proposed hardware circuit is optimized
to be bounded to the smallest efficient size to minimize the area and the critical
path delay. The proposed design was coded in VHDL, implemented on the
Virtex-6 FPGA, and its performance was analyzed utilizing XILINX ISE
tools. Our design occupies the smallest area comparing with other
implementations on the same FPGA type. The proposed design saves in a
range between 60.0% and 99.0% of the resources compared with other relevant
designs.
A Review of Different Methods for Booth MultiplierIJERA Editor
In this review paper, different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processor, so designing a high-speed multiplier is the need of the hour. Advantages of using modified booth multiplier algorithm is that the number of partial product is reduced. Different types of addition algorithms are also discussed which are used for addition operation of multiplier.
International Journal of Computational Engineering Research(IJCER)ijceronline
This document summarizes a research paper on designing a high-speed arithmetic architecture for a parallel multiplier-accumulator based on the radix-2 modified Booth algorithm. It presents the design of a modified Booth multiplier using a carry lookahead adder for high accuracy with a fixed width. It also proposes a high-speed MAC architecture that improves performance by eliminating the accumulator and modifying the carry-save adder to add lower bits in advance, reducing the number of inputs to the final adder. The proposed CSA architecture can efficiently implement the operations of the new MAC arithmetic.
International Journal of Computational Engineering Research(IJCER)ijceronline
This document summarizes a research paper on designing a high-speed arithmetic architecture for a parallel multiplier-accumulator based on the radix-2 modified Booth algorithm. It presents the design of a modified Booth multiplier using a carry lookahead adder for high accuracy with a fixed width. It also proposes a high-speed MAC architecture that improves performance by eliminating the accumulator and modifying the carry-save adder to add lower bits in advance, reducing the number of inputs to the final adder. The proposed CSA architecture can efficiently implement the operations of the new MAC arithmetic.
This document discusses matrix inversion techniques for MIMO wireless communication systems. It begins by introducing how matrix inversion is used in algorithms for MIMO systems and standards like 802.11n. Existing matrix inversion approaches cannot achieve the performance needed for real-time 802.11n systems. The document then presents a new matrix inversion algorithm based on modified squared Givens rotations (MSGR) that enables real-time implementation with high throughput and low latency. This algorithm overcomes limitations of other QR decomposition techniques. Finally, the document evaluates this algorithm integrated into a MIMO receiver and demonstrates it can support the requirements of modern wireless standards like 802.11n.
Parallel Processing Technique for Time Efficient Matrix MultiplicationIJERA Editor
The document proposes a parallel-parallel input single output (PPI-SO) design for matrix multiplication that reduces hardware resources compared to existing designs. It uses fewer multipliers and registers than existing designs, trading off increased completion time. Simulation results show the PPI-SO design uses 30% less energy and involves 70% less area-delay product than other designs.
Similar to Efficient implementation of bit parallel finite (20)
Mechanical properties of hybrid fiber reinforced concrete for pavementseSAT Journals
Abstract
The effect of addition of mono fibers and hybrid fibers on the mechanical properties of concrete mixture is studied in the present
investigation. Steel fibers of 1% and polypropylene fibers 0.036% were added individually to the concrete mixture as mono fibers and
then they were added together to form a hybrid fiber reinforced concrete. Mechanical properties such as compressive, split tensile and
flexural strength were determined. The results show that hybrid fibers improve the compressive strength marginally as compared to
mono fibers. Whereas, hybridization improves split tensile strength and flexural strength noticeably.
Keywords:-Hybridization, mono fibers, steel fiber, polypropylene fiber, Improvement in mechanical properties.
Material management in construction – a case studyeSAT Journals
Abstract
The objective of the present study is to understand about all the problems occurring in the company because of improper application
of material management. In construction project operation, often there is a project cost variance in terms of the material, equipments,
manpower, subcontractor, overhead cost, and general condition. Material is the main component in construction projects. Therefore,
if the material management is not properly managed it will create a project cost variance. Project cost can be controlled by taking
corrective actions towards the cost variance. Therefore a methodology is used to diagnose and evaluate the procurement process
involved in material management and launch a continuous improvement was developed and applied. A thorough study was carried
out along with study of cases, surveys and interviews to professionals involved in this area. As a result, a methodology for diagnosis
and improvement was proposed and tested in selected projects. The results obtained show that the main problem of procurement is
related to schedule delays and lack of specified quality for the project. To prevent this situation it is often necessary to dedicate
important resources like money, personnel, time, etc. To monitor and control the process. A great potential for improvement was
detected if state of the art technologies such as, electronic mail, electronic data interchange (EDI), and analysis were applied to the
procurement process. These helped to eliminate the root causes for many types of problems that were detected.
Managing drought short term strategies in semi arid regions a case studyeSAT Journals
Abstract
Drought management needs multidisciplinary action. Interdisciplinary efforts among the experts in various fields of the droughts
prone areas are helpful to achieve tangible and permanent solution for this recurring problem. The Gulbarga district having the total
area around 16, 240 sq.km, and accounts 8.45 per cent of the Karnataka state area. The district has been situated with latitude 17º 19'
60" North and longitude of 76 º 49' 60" east. The district is situated entirely on the Deccan plateau positioned at a height of 300 to
750 m above MSL. Sub-tropical, semi-arid type is one among the drought prone districts of Karnataka State. The drought
management is very important for a district like Gulbarga. In this paper various short term strategies are discussed to mitigate the
drought condition in the district.
Keywords: Drought, South-West monsoon, Semi-Arid, Rainfall, Strategies etc.
Life cycle cost analysis of overlay for an urban road in bangaloreeSAT Journals
Abstract
Pavements are subjected to severe condition of stresses and weathering effects from the day they are constructed and opened to traffic
mainly due to its fatigue behavior and environmental effects. Therefore, pavement rehabilitation is one of the most important
components of entire road systems. This paper highlights the design of concrete pavement with added mono fibers like polypropylene,
steel and hybrid fibres for a widened portion of existing concrete pavement and various overlay alternatives for an existing
bituminous pavement in an urban road in Bangalore. Along with this, Life cycle cost analyses at these sections are done by Net
Present Value (NPV) method to identify the most feasible option. The results show that though the initial cost of construction of
concrete overlay is high, over a period of time it prove to be better than the bituminous overlay considering the whole life cycle cost.
The economic analysis also indicates that, out of the three fibre options, hybrid reinforced concrete would be economical without
compromising the performance of the pavement.
Keywords: - Fatigue, Life cycle cost analysis, Net Present Value method, Overlay, Rehabilitation
Laboratory studies of dense bituminous mixes ii with reclaimed asphalt materialseSAT Journals
Abstract
The issue of growing demand on our nation’s roadways over that past couple of decades, decreasing budgetary funds, and the need to
provide a safe, efficient, and cost effective roadway system has led to a dramatic increase in the need to rehabilitate our existing
pavements and the issue of building sustainable road infrastructure in India. With these emergency of the mentioned needs and this
are today’s burning issue and has become the purpose of the study.
In the present study, the samples of existing bituminous layer materials were collected from NH-48(Devahalli to Hassan) site.The
mixtures were designed by Marshall Method as per Asphalt institute (MS-II) at 20% and 30% Reclaimed Asphalt Pavement (RAP).
RAP material was blended with virgin aggregate such that all specimens tested for the, Dense Bituminous Macadam-II (DBM-II)
gradation as per Ministry of Roads, Transport, and Highways (MoRT&H) and cost analysis were carried out to know the economics.
Laboratory results and analysis showed the use of recycled materials showed significant variability in Marshall Stability, and the
variability increased with the increase in RAP content. The saving can be realized from utilization of recycled materials as per the
methodology, the reduction in the total cost is 19%, 30%, comparing with the virgin mixes.
Keywords: Reclaimed Asphalt Pavement, Marshall Stability, MS-II, Dense Bituminous Macadam-II
Laboratory investigation of expansive soil stabilized with natural inorganic ...eSAT Journals
This document summarizes a study on stabilizing expansive black cotton soil with the natural inorganic stabilizer RBI-81. Laboratory tests were conducted to evaluate the effect of RBI-81 on the soil's engineering properties. The tests showed that with 2% RBI-81 and 28 days of curing, the unconfined compressive strength increased by around 250% and the CBR value improved by approximately 400% compared to the untreated soil. Overall, the study found that RBI-81 effectively improved the strength properties of the black cotton soil and its suitability as a soil stabilizer was supported.
Influence of reinforcement on the behavior of hollow concrete block masonry p...eSAT Journals
Abstract
Reinforced masonry was developed to exploit the strength potential of masonry and to solve its lack of tensile strength. Experimental
and analytical studies have been carried out to investigate the effect of reinforcement on the behavior of hollow concrete block
masonry prisms under compression and to predict ultimate failure compressive strength. In the numerical program, three dimensional
non-linear finite elements (FE) model based on the micro-modeling approach is developed for both unreinforced and reinforced
masonry prisms using ANSYS (14.5). The proposed FE model uses multi-linear stress-strain relationships to model the non-linear
behavior of hollow concrete block, mortar, and grout. Willam-Warnke’s five parameter failure theory has been adopted to model the
failure of masonry materials. The comparison of the numerical and experimental results indicates that the FE models can successfully
capture the highly nonlinear behavior of the physical specimens and accurately predict their strength and failure mechanisms.
Keywords: Structural masonry, Hollow concrete block prism, grout, Compression failure, Finite element method,
Numerical modeling.
Influence of compaction energy on soil stabilized with chemical stabilizereSAT Journals
This document summarizes a study on the influence of compaction energy on soil stabilized with a chemical stabilizer. Laboratory tests were conducted on locally available loamy soil treated with a patented polymer liquid stabilizer and compacted at four different energy levels. The study found that increasing the compaction effort increased the density of both untreated and treated soil, but the rate of increase was lower for stabilized soil. Treating the soil with the stabilizer improved its unconfined compressive strength and resilient modulus, and reduced accumulated plastic strain, with these properties further improved by higher compaction efforts. The stabilized soil exhibited strength and performance benefits compared to the untreated soil.
Geographical information system (gis) for water resources managementeSAT Journals
This document describes a hydrological framework developed in the form of a Hydrologic Information System (HIS) to meet the information needs of various government departments related to water management in a state. The HIS consists of a hydrological database coupled with tools for collecting and analyzing spatial and non-spatial water resources data. It also incorporates a hydrological model to indirectly assess water balance components over space and time. A web-based GIS portal was created to allow users to access and visualize the hydrological data, as well as outputs from the SWAT hydrological model. The framework is intended to facilitate integrated water resources planning and management across different administrative levels.
Forest type mapping of bidar forest division, karnataka using geoinformatics ...eSAT Journals
Abstract
The study demonstrate the potentiality of satellite remote sensing technique for the generation of baseline information on forest types
including tree plantation details in Bidar forest division, Karnataka covering an area of 5814.60Sq.Kms. The Total Area of Bidar
forest division is 5814Sq.Kms analysis of the satellite data in the study area reveals that about 84% of the total area is Covered by
crop land, 1.778% of the area is covered by dry deciduous forest, 1.38 % of mixed plantation, which is very threatening to the
environmental stability of the forest, future plantation site has been mapped. With the use of latest Geo-informatics technology proper
and exact condition of the trees can be observed and necessary precautions can be taken for future plantation works in an appropriate
manner
Keywords:-RS, GIS, GPS, Forest Type, Tree Plantation
Factors influencing compressive strength of geopolymer concreteeSAT Journals
Abstract
To study effects of several factors on the properties of fly ash based geopolymer concrete on the compressive strength and also the
cost comparison with the normal concrete. The test variables were molarities of sodium hydroxide(NaOH) 8M,14M and 16M, ratio of
NaOH to sodium silicate (Na2SiO3) 1, 1.5, 2 and 2.5, alkaline liquid to fly ash ratio 0.35 and 0.40 and replacement of water in
Na2SiO3 solution by 10%, 20% and 30% were used in the present study. The test results indicated that the highest compressive
strength 54 MPa was observed for 16M of NaOH, ratio of NaOH to Na2SiO3 2.5 and alkaline liquid to fly ash ratio of 0.35. Lowest
compressive strength of 27 MPa was observed for 8M of NaOH, ratio of NaOH to Na2SiO3 is 1 and alkaline liquid to fly ash ratio of
0.40. Alkaline liquid to fly ash ratio of 0.35, water replacement of 10% and 30% for 8 and 16 molarity of NaOH and has resulted in
compressive strength of 36 MPa and 20 MPa respectively. Superplasticiser dosage of 2 % by weight of fly ash has given higher
strength in all cases.
Keywords: compressive strength, alkaline liquid, fly ash
Experimental investigation on circular hollow steel columns in filled with li...eSAT Journals
Abstract
Composite Circular hollow Steel tubes with and without GFRP infill for three different grades of Light weight concrete are tested for
ultimate load capacity and axial shortening , under Cyclic loading. Steel tubes are compared for different lengths, cross sections and
thickness. Specimens were tested separately after adopting Taguchi’s L9 (Latin Squares) Orthogonal array in order to save the initial
experimental cost on number of specimens and experimental duration. Analysis was carried out using ANN (Artificial Neural
Network) technique with the assistance of Mini Tab- a statistical soft tool. Comparison for predicted, experimental & ANN output is
obtained from linear regression plots. From this research study, it can be concluded that *Cross sectional area of steel tube has most
significant effect on ultimate load carrying capacity, *as length of steel tube increased- load carrying capacity decreased & *ANN
modeling predicted acceptable results. Thus ANN tool can be utilized for predicting ultimate load carrying capacity for composite
columns.
Keywords: Light weight concrete, GFRP, Artificial Neural Network, Linear Regression, Back propagation, orthogonal
Array, Latin Squares
Experimental behavior of circular hsscfrc filled steel tubular columns under ...eSAT Journals
This document summarizes an experimental study that tested circular concrete-filled steel tube columns with varying parameters. 45 specimens were tested with different fiber percentages (0-2%), tube diameter-to-wall-thickness ratios (D/t from 15-25), and length-to-diameter (L/d) ratios (from 2.97-7.04). The results found that columns filled with fiber-reinforced concrete exhibited higher stiffness, equal ductility, and enhanced energy absorption compared to those filled with plain concrete. The load carrying capacity increased with fiber content up to 1.5% but not at 2.0%. The analytical predictions of failure load closely matched the experimental values.
Evaluation of punching shear in flat slabseSAT Journals
Abstract
Flat-slab construction has been widely used in construction today because of many advantages that it offers. The basic philosophy in
the design of flat slab is to consider only gravity forces; this method ignores the effect of punching shear due to unbalanced moments
at the slab column junction which is critical. An attempt has been made to generate generalized design sheets which accounts both
punching shear due to gravity loads and unbalanced moments for cases (a) interior column; (b) edge column (bending perpendicular
to shorter edge); (c) edge column (bending parallel to shorter edge); (d) corner column. These design sheets are prepared as per
codal provisions of IS 456-2000. These design sheets will be helpful in calculating the shear reinforcement to be provided at the
critical section which is ignored in many design offices. Apart from its usefulness in evaluating punching shear and the necessary
shear reinforcement, the design sheets developed will enable the designer to fix the depth of flat slab during the initial phase of the
design.
Keywords: Flat slabs, punching shear, unbalanced moment.
Evaluation of performance of intake tower dam for recent earthquake in indiaeSAT Journals
Abstract
Intake towers are typically tall, hollow, reinforced concrete structures and form entrance to reservoir outlet works. A parametric
study on dynamic behavior of circular cylindrical towers can be carried out to study the effect of depth of submergence, wall thickness
and slenderness ratio, and also effect on tower considering dynamic analysis for time history function of different soil condition and
by Goyal and Chopra accounting interaction effects of added hydrodynamic mass of surrounding and inside water in intake tower of
dam
Key words: Hydrodynamic mass, Depth of submergence, Reservoir, Time history analysis,
Evaluation of operational efficiency of urban road network using travel time ...eSAT Journals
This document evaluates the operational efficiency of an urban road network in Tiruchirappalli, India using travel time reliability measures. Traffic volume and travel times were collected using video data from 8-10 AM on various roads. Average travel times, 95th percentile travel times, and buffer time indexes were calculated to assess reliability. Non-motorized vehicles were found to most impact reliability on one road. A relationship between buffer time index and traffic volume was developed. Finally, a travel time model was created and validated based on length, speed, and volume.
Estimation of surface runoff in nallur amanikere watershed using scs cn methodeSAT Journals
Abstract
The development of watershed aims at productive utilization of all the available natural resources in the entire area extending from
ridge line to stream outlet. The per capita availability of land for cultivation has been decreasing over the years. Therefore, water and
the related land resources must be developed, utilized and managed in an integrated and comprehensive manner. Remote sensing and
GIS techniques are being increasingly used for planning, management and development of natural resources. The study area, Nallur
Amanikere watershed geographically lies between 110 38’ and 110 52’ N latitude and 760 30’ and 760 50’ E longitude with an area of
415.68 Sq. km. The thematic layers such as land use/land cover and soil maps were derived from remotely sensed data and overlayed
through ArcGIS software to assign the curve number on polygon wise. The daily rainfall data of six rain gauge stations in and around
the watershed (2001-2011) was used to estimate the daily runoff from the watershed using Soil Conservation Service - Curve Number
(SCS-CN) method. The runoff estimated from the SCS-CN model was then used to know the variation of runoff potential with different
land use/land cover and with different soil conditions.
Keywords: Watershed, Nallur watershed, Surface runoff, Rainfall-Runoff, SCS-CN, Remote Sensing, GIS.
Estimation of morphometric parameters and runoff using rs & gis techniqueseSAT Journals
This document summarizes a study that used remote sensing and GIS techniques to estimate morphometric parameters and runoff for the Yagachi catchment area in India over a 10-year period. Morphometric analysis was conducted to understand the hydrological response at the micro-watershed level. Daily runoff was estimated using the SCS curve number model. The results showed a positive correlation between rainfall and runoff. Land use/land cover changes between 2001-2010 were found to impact estimated runoff amounts. Remote sensing approaches provided an effective means to model runoff for this large, ungauged area.
Effect of variation of plastic hinge length on the results of non linear anal...eSAT Journals
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Efficient implementation of bit parallel finite
1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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EFFICIENT IMPLEMENTATION OF BIT PARALLEL FINITE
FIELD MULTIPLIERS
Ajitha.S.S1
, Retheesh.D2
1
ME, Department of ECE, St.Xavier’s Catholic College of Engineering, Tamilnadu, India
2
Assistant Professor, Department of CSE, Saveetha Engineering College, Tamilnadu, India
Abstract
Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition
and multiplication are the two basic operations in the finite field GF (2m
).The finite field multiplication is the most resource and time
consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba
Multiplier over GF (2m
) is presented. This is especially interesting for high performance systems because of its carry free property. To
reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m
) based on Karatsuba Multiplier is used. The
LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel
Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the
bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation.
Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
----------------------------------------------------------------------***------------------------------------------------------------------------
1. INTRODUCTION
A finite field or Galois field is a field that contains only
finitely many elements. The finite fields are classified by size.
This classification specifies the order of the field. Notations
for the finite fields are GF (pm
) or Fp
m
, where the letters ―GF‖
stand for ―Galois field‖. The order or cardinal or number of
elements, of a finite field is of the form pm,
where p is a prime
number called the characteristic of the field and m is a positive
integer called the dimension of the field. Finite field arithmetic
operations in GF (2m
) were frequently desired in coding
theory, cryptography, digital signal processing. Coding theory
is an approach to various science disciplines such as
information theory, electrical engineering, data transmission,
mathematics and science, which helps design efficient and
reliable data transmission methods so that redundancy can be
removed and errors corrected.
Applications of cryptography include ATM cards, computer
passwords and e-commerce. Cryptography is the practice and
study of hiding information. Modern cryptography intersects
the disciplines of mathematics, computer science and
engineering. In these applications, multiplication is the most
common arithmetic. Thus it is desirable to design hardware-
efficient multiplier for GF (2m
) to meet the real time
requirement with minimum hardware complexity.
There are three popular types of bases over finite fields:
polynomial basis (PB), normal basis (NB) and dual basis
(DB). Basis is a set of vectors that, in a linear combination,
can represent every vector in a given vector space. Polynomial
basis is a mathematical function that is the sum of a number of
terms. Normal basis in field theory is a special kind of basis
for Galois extensions of finite degree, characterized as a
forming a single orbit for the Galois group. Dual basis is a set
of vectors that forms a basis for the dual space of a vector
space. One advantage of the normal basis is that the squaring
of an element is computed by a cyclic shift of the binary
representation. The dual basis multipliers require less chip
area than other two types.
The polynomial basis multipliers are widely used and lead to
efficient implementations of multipliers. As compared to other
two bases multipliers, the polynomial basis multipliers have
low design complexity and their sizes are easier to extend to
meet various applications due to their simplicity, regularity,
and modularity in architecture. It appears that polynomial
multipliers for classes of trinomials still achieve the lowest
circuit complexity
Arithmetic operations such as addition and multiplication are
the two basic operations in the finite field GF (2m
). Addition in
GF (2m
) is easily realized using m two-input XOR gates while
multiplication is costly in terms of gate count and time delay.
The other operations of finite fields, such as exponentiation,
division and inversion can be performed by repeated
multiplications. As a result there is a need to have fast
multiplication architecture with low complexity.
The hardware/software implementation efficiency of finite
field arithmetic is measured in terms of the associated space
and time complexities. The space complexity is defined as the
number of XOR and AND gates needed for the
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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implementation of the circuit. The space and time
complexities of a multiplier heavily depend on how the field
elements are represented. Finite field multipliers with different
bases of representation have been realized to be used for
various applications. The polynomial basis multipliers are
more efficient and more widely used compared with
multipliers in the other bases of representations.
1.1 Related Work
C.Grabbe,M.Bednara,J.Teich, [1] presented four high
performance GF(2233) multipliers for an FPGA realization
and analyzed the time and area complexities. The finite field
elements are represented as polynomial basis and normal
basis. In polynomial basis, classical multiplier and Karatsuba
multipliers were designed.The advantage of classical
multiplier is regular structure and pipelined operation.The
disadvantage is high space complexity. In Karatsuba
multiplier the advantage is less number of gates are
required.The normal basis multipliers are Massey-Omura and
Sunar-Koc multiplier. The advantage of Massey-Omura is
high flexibility and Sunar-Koc is total number of gates are
reduced.
P.L.Montgomery,[2] presented Karatsuba Ofman algorithm
for multiplying two polynomials. Here multiplication of 5-
term, 6-term and 7-term polynomials are provided with scalar
multiplication of 13,17 and 22.Using 6-term polynomial only
leads to better asymptotic performance than standard
karatsuba.
C.Paar, [3] presented a new bit parallel structure for a
multiplier with low space complexity in Galois field is
introduced. Finite field of GF(2n
) is considered and field
extension of GF((2n
)m
). The field elements are represented in
the canonical base or in standard basis. Field of the form
GF((2n
)m
) are referred as composite field. Karatsuba Ofman
algorithm is used to multiply two polynomials effectively.
Advantages are complexity is reduced by introducing the
composite field. The main disadvantage is security is less and
does not have a regular structure.
C.Rebeirno and D.Mukhopadhyay, [4] presented a hybrid
technique which has a better area delay product. Masking
strategies are introduced to prevent power based side channel
attacks on the multiplier. SCAs are the biggest threat to
modern cryptography systems. In basic recursive KM, the
number LUTs required to combine the partial products is
much lower but it cannot applied directly to ECC. The hybrid
KM requires least resources as compared to other KMs used
for elliptic curve arithmetic; also it has a unique architecture.
Demerits are it is not efficient for FPGA platform as the
number of utilized LUTs is 65%.
A.Reyhani-Masoleh and A.Hasan, [5] presented a new bit
parallel structure for the polynomial basis multiplication
which is applicable to all type of irreducible binary
polynomial. The main advantage of this new formulation is
that it can be used with any field defining irreducible
polynomial. Then a bit parallel hardware architecture
generalization is provided. The architecture consist of two
parts IP network and Q network. The space and time
complexities are analysed as a function of reduction matrix Q.
the main advantage is only fewer number of lines are required
on the bus.
F.Rodriguez and C.K.Koc,[6] presented the Karatsuba-
Ofman Algorithm in which the degree of defining the
irreducible polynomial can be arbitrarily selected by the
designer allowing the usage of prime degrees. Here finite field
and composite field are considered. Composite multiplication
is performed by n-bit Karatsuba multiplier. The main
advantage is number of multiplication is reduced. The
composite field multiplication is performed by binary
Karatsuba multipliers. The advantage is improved gate
complexity .The disadvantage is wastage of several arithmetic
operation.
B.Sunar,[7] presented the subquadratic complexity multipliers
for even characteristic field extension. A short convolution
algorithm named Winograd short convolution algorithm were
designed to improve the space and time complexity. A certain
Winograd short convolutional algorithm is essentially
identical to the Karatsuba algorithm. The merits of Winograd
techniques are it can be easily built for any desired length; it is
simple and uniform construction. The main disadvantages are
appears to have less structure and cause additional wire delay
in VLSI implementation.
A.Weimerskirch and C.Paar, [8] presented the classical
Karatsuba algorithm for polynomial multiplication. Three
methods considered are digital method, Fast Fourier transform
method and Karatsuba method. The Karatsuba algorithm is
derived in two ways namely Chinese Remainder Theorem and
Simple Algebraic Transform KA is applied recursively if the
degree of polynomial is 2i
, where i>1 is a positive integer.
Advantage- squaring the polynomial is easily performed;
adding a dummy coefficients the complexity is reduced.
Disadvantage is a number of intermediate results have been
stored due to the recursive nature of KA.
J.VonzurGathen and J.Shokrollahi, [9] presented different
possibilities for implementing the Karatsuba multiplier for
polynomials over F2 on FPGA. Classical multiplier, Karatsuba
multiplier and a hybrid design were provided. The Karatsuba
multiplier has the lowest crossover point with the classical
algorithm. In hardware, the algorithmic and platform
dependent optimizations yield efficient designs. The resources
usage of polynomial multipliers is decreased by using both the
algorithmic and platform dependent method. The hybrid
design is used to minimize the total arithmetic cost and results
in significant area savings.
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G.Zhou, H.Michalik and L.Hinsenkamp, [10] addresses the
efficient and high throughput implementations of AES-GSM
optimized for FPGAs. The two main components in GCM are
an AES engine and a finite field multiplier over GF (2128
).The
complexity analysis presented is based on FPGA primitives
(LUTs). Modular multiplication consists of two steps: first a
classical multiplication and then a modular reduction. The
straight forward multiplier is used to get speed efficient design
while a Karatsuba multiplier is used to get an area efficient
design. Merits are reduced hardware complexity and high
throughput.
2. FINITE FIELD ARITHMETIC
Arithmetic in a finite field is different from standard integer
arithmetic. There are limited numbers of elements in the finite
field; all operations performed in the finite fields result in an
element within that field. While each finite field itself is not
infinite, there are infinitely many different finite fields; their
number of elements is necessarily of the form pn
. and the two
finite fields of the same size are isomorphic. An element α in
GF (2m
) can be represented as a polynomial, where αi € GF
(2m
).
Addition of two elements in GF (2m
) is performed as
polynomial addition in
GF (2m
)
Where + is XOR operation.
2.1 Addition and Multiplication In Finite Field
Addition and subtraction are performed by adding or
subtracting two of these polynomials together, and reducing
the result modulo the characteristic. In a finite field with
characteristic 2, addition and subtraction are identical, and are
accomplished using the XOR operator. When two polynomials
are added, each term is added independently; there is no
concept of a carry from one term to another.
Thus, Polynomial:
(x6
+ x4
+ x + 1) + (x7
+ x6
+ x3
+ x) = x7
+ x4
+ x3
+ 1
Binary: {01010011} + {11001010} = {10011001}
Hexadecimal: {53} + {CA} = {99}
Notice that under regular addition of polynomials, the sum
would contain a term 2x6
, but that this term becomes 0x6
and is
dropped when the answer is reduced modulo 2.
In binary representation, the coefficients can be only 1 or
0.When adding the coefficients, the following rule applies:
o 0+0=0
o 0+1=1
o 1+0=1
o 1+1=0(there is no carry)
Table-1: Polynomial Addition
Table-1 shows both the normal algebraic sum and the
characteristic 2 finite field sum of a few polynomials:
In computer science applications, the operations are simplified
for finite fields of characteristic 2, also called GF(2n
) Galois
fields, making these fields especially popular choices for
applications. The same logic that made addition become XOR
also applies to subtraction. The exclusive OR operation is
easier for digital logic than binary additions.
Multiplication in a finite field is multiplication modulo an
irreducible reducing polynomial used to define the finite field.
(i.e., it is multiplication followed by division using the
reducing polynomial as the divisor—the remainder is the
product.) The symbol "•" may be used to denote multiplication
in a finite field. Example: Rijndael's finite field
Rijndael uses a characteristic 2 finite field with 8 terms, which
can also be called the Galois field GF (28
). It employs the
following reducing polynomial for multiplication:
x8
+ x4
+ x3
+ x + 1.
For example, {53} • {CA} = {01} in Rijndael's field because
(x6
+ x4
+ x + 1)(x7
+ x6
+ x3
+ x) =
x13
+ x12
+ x9
+ x7
+ x11
+ x10
+ x7
+ x5
+ x8
+ x7
+ x4
+ x2
+ x7
+
x6
+ x3
+ x =
p1 p2
p1 + p2 (normal
algebra)
p1 + p2 in GF(2n
)
x3
+ x + 1 x3
+ x2
2x3
+ x2
+ x + 1 x2
+ x + 1
x4
+ x2
x6
+ x2
x6
+ x4
+ 2x2
x6
+ x4
x + 1 x2
+ 1 x2
+ x + 2 x2
+ x
x3
+ x x2
+ 1 x3
+ x2
+ x + 1 x3
+ x2
+ x + 1
x2
+ x x2
+ x 2x2
+ 2x 0
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x13
+ x12
+ x9
+ x11
+ x10
+ x5
+ x8
+ x4
+ x2
+ x6
+ x3
+ x =
x13
+ x12
+ x11
+ x10
+ x9
+ x8
+ x6
+ x5
+ x4
+ x3
+ x2
+ x
And
x13
+ x12
+ x11
+ x10
+ x9
+ x8
+ x6
+ x5
+ x4
+ x3
+ x2
+ x
modulo x8
+ x4
+ x3
+ x + 1 = (11111101111110 mod
100011011) = 1, which can be performed through long
division method
2.2 Classical Multiplier
The Classical multiplier is the simplest multiplier to perform
finite field multiplication. It is also called as paper and pencil
method or traditional method. To perform the classical
multiplication it requires only AND gates and XOR gates. The
number of AND gates required is n2
and (n-1)2
XOR gates,
where n is bit depth. The total gate complexity is 2n2
-1 and the
time complexity is TAND+(log2n)TXOR. Figure 1 shows the
calculation of the product of two 4-bit integer numbers given
by A3A2A1A0 (multiplicand) and B3B2B1B0 (multiplier).
A3 A2 A1 A0
B3 B2 B1 B0
A3.B0 A2.B0 A1.B0 A0.B0
A3.B1 A2.B1 A1.B1 A0.B1
A3.B2 A2.B2 A1.B2 A0.B2
A3.B3 A2.B3 A1.B3 A0.B3
S6 S5 S4 S3 S2 S1 S0
Fig-1: 4-bit multiplication
Each of the ANDed terms is referred to as a partial product.
The final product is obtained by summing each column of
partial products and is implemented using half adders.. If carry
comes, it must be propagated from the right to the left across
the columns. Adder that accepts a carry from the right must be
a full adder. 4-bit classical multiplier is shown in figure 2.
Fig -2 4-bit Classical Multiplier
The classical multiplier consists of AND gates, Full Adders
and Half adders. The 16 AND gates forms the sixteen partial
products. It is formed by ANDing all combinations of the four
multiplier bits with the four multiplicand bits. The column
sums are obtained using a combination of half and full adders.
The half adder blocks accept two bits to be added from the
top, carry out exits from the left of each block. The output
from the bottom of a block is the sum. The full adder accepts
two bits to be added from the top, any carry in from the right
and carryout exist from left of each block. The bottom of each
block gives the output. The least significant output bit, S0 is
computed as the product of two input bits A0 and B0.This
operation cannot generate a carry out. The next output bit, S1,
involves the sum of two partial products. A half adder is used
to form the sum since there can be no carry in from the first
column.
The third output bit, S2, is formed from the sum of three (1-
bit) partial products plus a possible carry in from the previous
bit. This operation requires two cascaded adders to sum the
four possible input bits (three partial products and one possible
carry in from the right). The remaining output bits are formed
similarly.
2.3 Karatsuba Multiplier
The Karatsuba algorithm is an efficient multiplication
algorithm. It reduces the multiplication of two n-digit numbers
to at most single digit multiplications. It is the fast
multiplication algorithm and at the same time it is the fast
computational algorithm. It uses the technique divide and
conquer technique. That is Karatsuba algorithm is applied to
large degree polynomials by splitting it into a lower and an
upper half. The algorithm becomes recursive if its applied
again to multiply these polynomial half’s.
The next iteration step splits these polynomial again in half.
The algorithm eventually terminates after t-steps. In the final
step the polynomial degenerates into single coefficients. This
recursive splitting of polynomials and the special reassembling
of the partial products ,drastically reduces the number of AND
gates to nlog
2
3
or n1.59
but the n umber of XOR gates increased
to 6nlog
2
3
-8n+2 which is very efficient when the polynomials
become large. But in GF(2n
), multiplication is a quite
expensive operation and an addition can be performed at
nearly no costs(since an XOR is very small on an FPGA and
no carry bits exist) .
For the modular multiplier, the straight forward multiplication
is used to get a speed efficient design, while the karatsuba
algorithm is used to get an area efficient design. But by
combining classical and Karatsuba, we get a high performance
and highly efficient multipliers. Squaring can be easily
performed by applying Karatsuba algorithm.
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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In general consider two polynomials of degree m-1
m-1 m-1 m/2-1
A = ∑ αixi
= ∑ αixi
+ ∑ αixi
i=0 i=m/2 i=0
m/2-1 m/2-1
= xm/2
∑ αi+m/2xi
+ ∑ αixi
= xm/2
AH
+AL
i=0 i=0
and
m-1 m-1 m/2-1
B = ∑ bixi
= ∑ bixi
+ ∑ bixi
i=0 i=m/2 i=0
m/2-1 m/2-1
=xm/2
∑ bi+m/2xi
+ ∑ bixi
= xm/2
BH
+BL
i=0 i=0
The polynomial product is
C=xm
AH
BH
+(AH
BL
+AL
BH
) x(m/2)
+ AL
BL
.
To perform an n-bit multiplication we need an algorithm that
divides the n-bit multiplication into several one bit
multiplications, which are the only multiplications that can be
computed directly (i.e., by an AND-gate). With Karatsuba’s
divide and conquer multiplication algorithm, a multiplication
of two n-bit polynomials can be computed with three n=2-bit
multiplications and some additions (which are XOR’s in our
case) to determine interim results and accumulate the final
result. If n is four or more, the three multiplications in
Karatsuba's basic step involve operands with less than n digits.
Therefore, those products can be computed by recursive calls
of the Karatsuba algorithm. Figure 3 denotes 1-bit polynomial
karatsuba multiplier. ―.‖denotes multiplication in finite field.
Fig-3: one bit polynomial Karatsuba multiplier
Fig-4: 2- bit polynomial Karatsuba multiplier
Figure 4 shows the two bit polynomial Karatsuba multiplier
KM2.Here the dot represents the finite field multiplication
(AND gate ) and the plus represents the addition(XOR
gate).The two bit polynomial is derived from three one bit
polynomial Karatsuba multiplier KM1 in addition some
XOR gates are also used. Here a0,a1,b0,b1 are the coefficients
of the one degree polynomial and it is given as input to KM2 ;
c0,c1,c2 are the output of KM2.In normal classical multipliers
requires 4 AND gates and 3 XOR gates. But in Karatsuba
multiplier requires only 3 AND gates and 4 XOR gates. Thus
the space complexity of the multiplier is reduced.
Fig-5: 4- bit polynomial Karatsuba multiplier
6. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Figure 5 shows the 4- bit polynomial Karatsuba multiplier
KM4. Here the dot represents the finite field multiplication
(AND gate) and the plus represents the addition (XOR gate).
The 4-bit polynomial is derived from three 2-bit polynomial
Karatsuba multiplier KM2 in addition some XOR gates are
also used.
3. RESULTS
In this paper, finite field multipliers are developed and is
simulated using Xilinx ISE 8.1i in Verilog. It is synthesized
using Xiinx Virtex 4, device Xe3VS500E (package FT250,
speed grade -4) and the comparison results are extracted from
the synthesis report.
The simulated waveform for the classical multiplier is shown
in figure 6. Here the inputs are a= 0101 and b= 1000. The
output is c=101000.
Fig-6: simulated waveform for classical multiplier
The simulated Waveform for Karatsuba Multiplier is shown in
figure 7. The inputs given area=1111 and b=0100. The output
is c=111100
Fig-7: simulated waveform for Karatsuba multiplier
Table-2: Comparison of 4-bit Multipliers
Multiplier
No.of 4-input
LUTs
Total Memory Usage
(kb)
No.of Slices
Delay
(ns)
No. of bonded
IOBs
Classical Multiplier 29 118448 17 13.812 16
Karatsuba Multiplier 11 117424 6 7.563 15
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Table 2 shows the comparative results of both classical and
Karatsuba multipliers. From the table, karatsuba multiplier
consumes less space than the classical multiplier.
4. CONCLUSIONS
Finite field multipliers play a very important role in the areas
of digital communication especially in the areas of
cryptography, error control coding and digital signal
processing. In this paper, two multipliers namely classical and
Karatsuba multipliers were simulated. The comparison results
show that Karatsuba multiplier is more efficient than the other
multiplier. Using Karatsuba multiplier we can improve the
performance of the process. The Karatsuba algorithm is an
optimization technique used for decomposing larger
multiplications into multiple smaller multiplications. This
feature allows the multiplier to be scaled easily.
REFERENCES
[1]. C.Grabbe,M.Bednara,J.Teich,J.von zur Gathen, and
J.Shokrollahi,‖FPGA designs of parallel high performance
GF(2233
) multipliers,‖ in Proc.Int.Symp.Circuits
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