Skanda M J is seeking opportunities in VLSI design, verification, and automation. He has a Master's in VLSI Design from Vellore Institute of Technology with a CGPA of 8.29. His projects include investigating memristor crossbar array architecture, implementing delta sigma ADCs, designing low power adders and a BCD adder using carry select correction. He has experience in EDA tools like Cadence and experience working as a transaction risk investigator.