尊敬的 微信汇率:1円 ≈ 0.046166 元 支付宝汇率:1円 ≈ 0.046257元 [退出登录]
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1
CURRICULUM VITAE
Current Location: New Delhi (NCR) Tel:+919582400356 Email:sumitscientist37@gmail.com
Sumit Sharma
Objective
Wish to serve an organization in VLSI Domain and Embedded domain which provides me
sample opportunities to grow and contribute to the better world by creating value together with a
vision for the future.
Educational Qualifications
M. Tech.
B. Tech.
ITM University , Gurgaon , Haryana
Institute Of Engineering And Technology , Alwar
(affiliated to RTU,Kota)
2013-2015
2008-2012
High School SBV , Palam(affiliated to CBSE Board ) 2007-2008
Matriculation SBV , Palam(affiliated to CBSE Board) 2005-2006
Skills
 Sequential Language
C, C++ language, Verilog , System Verilog
 Operating system
Windows 7,Linux(Red Hat),Windows Xp
Project Work
 Energy saver using microcontroller 8051: Basically it was controlling switching of A.C
appliances using relay.
 Moving message display system using 8051: It was just a wireless message display
technique using Sim module and microcontroller.
 FPGA Implementation of Booth Multiplier using Verilog.
 Verification of Synchronous FIFO with SystemVerilog.
 Advanced encryption standard 128 bit key using Verilog.
 Thesis project advanced encryption standard 256 bit key using vhdl.
Training Associates
MTNL , New Delhi
Xinoe Pvt. Ltd , Gurgaon
Tevatron technologies pvt.
Ltd
: GSM, CDMA, Switching System, Optical Fibre.
: System Verilog Verification using UVM 1.1
: Verilog and Vhdl, System Verilog, etc.
2
Seminars/Workshops
 Seminar delivered on “Transparent Electronics”.
 Attended the seminar on “ CYBER CRIME “
 Attended a value added program on Linux scripting.
 Attended a workshop on Linux.
 Attended a 5 day workshop on ethical hacking and securities.
 Attended a workshop on robotics.
Area of Interest
 RTL Design and Verification
 Digital VLSI Design
 EDA Tool designing
personal Traits
1. Innovative Thinker
2. Goal Focused
3. Quick Learner
4. Leadership quality
References
Neeraj Kr. Shukla Professor
Department of EECE
ITM University
HUDA Sector-23A,
Gurgaon-122017 (Haryana) India
E-Mail: neerajkshukla@itmindia.edu
ContactNo. +91-9212628151
Personal Dossier
Date of Birth : 01th April 1991
Father's Name : Mr Rajesh Sharma
Languages known : English, Hindi.
Marital Status : Single
Sex : Male
Nationality : Indian
Address : D-208/40,MadhuVihar,Uttam Nagar
New Delhi,India 110059
Declaration:
I consider myself familiar with programming and scripting aspects. I am also confident of my
ability to work in a team and be an asset to your company.
3
I hereby declare that the information furnished above is true to best of my knowledge.
Place: New Delhi (Sumit Sharma)

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lat sumit res

  • 1. 1 CURRICULUM VITAE Current Location: New Delhi (NCR) Tel:+919582400356 Email:sumitscientist37@gmail.com Sumit Sharma Objective Wish to serve an organization in VLSI Domain and Embedded domain which provides me sample opportunities to grow and contribute to the better world by creating value together with a vision for the future. Educational Qualifications M. Tech. B. Tech. ITM University , Gurgaon , Haryana Institute Of Engineering And Technology , Alwar (affiliated to RTU,Kota) 2013-2015 2008-2012 High School SBV , Palam(affiliated to CBSE Board ) 2007-2008 Matriculation SBV , Palam(affiliated to CBSE Board) 2005-2006 Skills  Sequential Language C, C++ language, Verilog , System Verilog  Operating system Windows 7,Linux(Red Hat),Windows Xp Project Work  Energy saver using microcontroller 8051: Basically it was controlling switching of A.C appliances using relay.  Moving message display system using 8051: It was just a wireless message display technique using Sim module and microcontroller.  FPGA Implementation of Booth Multiplier using Verilog.  Verification of Synchronous FIFO with SystemVerilog.  Advanced encryption standard 128 bit key using Verilog.  Thesis project advanced encryption standard 256 bit key using vhdl. Training Associates MTNL , New Delhi Xinoe Pvt. Ltd , Gurgaon Tevatron technologies pvt. Ltd : GSM, CDMA, Switching System, Optical Fibre. : System Verilog Verification using UVM 1.1 : Verilog and Vhdl, System Verilog, etc.
  • 2. 2 Seminars/Workshops  Seminar delivered on “Transparent Electronics”.  Attended the seminar on “ CYBER CRIME “  Attended a value added program on Linux scripting.  Attended a workshop on Linux.  Attended a 5 day workshop on ethical hacking and securities.  Attended a workshop on robotics. Area of Interest  RTL Design and Verification  Digital VLSI Design  EDA Tool designing personal Traits 1. Innovative Thinker 2. Goal Focused 3. Quick Learner 4. Leadership quality References Neeraj Kr. Shukla Professor Department of EECE ITM University HUDA Sector-23A, Gurgaon-122017 (Haryana) India E-Mail: neerajkshukla@itmindia.edu ContactNo. +91-9212628151 Personal Dossier Date of Birth : 01th April 1991 Father's Name : Mr Rajesh Sharma Languages known : English, Hindi. Marital Status : Single Sex : Male Nationality : Indian Address : D-208/40,MadhuVihar,Uttam Nagar New Delhi,India 110059 Declaration: I consider myself familiar with programming and scripting aspects. I am also confident of my ability to work in a team and be an asset to your company.
  • 3. 3 I hereby declare that the information furnished above is true to best of my knowledge. Place: New Delhi (Sumit Sharma)
  翻译: