This paper presents effects on MOS transistor performance due to scaling of its dimensions. Scaling theory deals with the change in the device characteristics with the decrease in the dimensions of a MOS transistor. MOS transistors are continuously scaled down due to the desire for high density and high functionality VLSI chips. The driving forces behind these developments are increasing the demand for portable systems requiring high throughput and high integration capacity. Effects of scaling on the performance characteristics of a MOS device are analyzed in this paper