The 8086 microprocessor is a 16-bit processor with a 20-bit address bus that can access up to 1MB of memory. It has 14 general purpose 16-bit registers and operates in minimum and maximum modes. In minimum mode, the 8086 provides all control signals for memory and I/O interfacing, including address/data bus lines, status lines, and control signals to indicate read/write operations and memory versus I/O access.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
This document provides an introduction to 8086 assembly language programming. It discusses program statements, data storage directives, defining and naming data, data transfer instructions, and the basic structure of an assembly language program, including segments for code, data, and stack. Pseudo-operations and directives are used to define variables and reserve memory. Data types like bytes, words, and doublewords are stored in reverse order in memory.
The document describes the Intel 8259 programmable interrupt controller chip. It contains blocks for buffering data to and from the system data bus, controlling read/write signals, storing interrupt requests in the interrupt request register, masking interrupts in the interrupt mask register, tracking interrupts being serviced in the in-service register, resolving interrupt priorities, and cascading multiple 8259 chips. The pin diagram shows inputs for interrupt requests, read/write control, an ID comparator for cascading, and an 8-bit data bus.
The Intel 80286 is the first microprocessor with memory management and protection abilities. It has a 16-bit data bus, 24-bit address bus, and can address up to 16MB of physical memory. Key features include virtual memory management, protection abilities through its integrated memory management unit, and two operating modes - real address mode and protected virtual address mode. The 80286 also introduced additional instructions for memory management and protection compared to earlier Intel processors.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
The document summarizes the Intel 80386 microprocessor, which was introduced in 1985. It discusses the key features and architecture of both the 80386DX and 80386SX versions. The 80386 was Intel's first 32-bit microprocessor and supported addressing up to 4GB of physical memory and 64TB of virtual memory using segmentation and paging. It had several operating modes and instruction sets to support multitasking and memory protection in protected mode.
The document discusses the input/output system of the Intel 80386 microprocessor. It has the following key points:
1. The 80386 I/O system is similar to previous Intel 8086 processors, with 64K bytes of I/O space available. Memory mapped I/O can also be implemented to access up to 4GB of I/O locations.
2. New features in the 80386 include I/O privilege information added to the task state segment for protected mode. I/O locations can also be blocked in protected mode to prohibit access.
3. Memory and I/O are controlled separately, with different control signals for reads and writes. Timing diagrams show the non-p
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
This document provides an introduction to 8086 assembly language programming. It discusses program statements, data storage directives, defining and naming data, data transfer instructions, and the basic structure of an assembly language program, including segments for code, data, and stack. Pseudo-operations and directives are used to define variables and reserve memory. Data types like bytes, words, and doublewords are stored in reverse order in memory.
The document describes the Intel 8259 programmable interrupt controller chip. It contains blocks for buffering data to and from the system data bus, controlling read/write signals, storing interrupt requests in the interrupt request register, masking interrupts in the interrupt mask register, tracking interrupts being serviced in the in-service register, resolving interrupt priorities, and cascading multiple 8259 chips. The pin diagram shows inputs for interrupt requests, read/write control, an ID comparator for cascading, and an 8-bit data bus.
The Intel 80286 is the first microprocessor with memory management and protection abilities. It has a 16-bit data bus, 24-bit address bus, and can address up to 16MB of physical memory. Key features include virtual memory management, protection abilities through its integrated memory management unit, and two operating modes - real address mode and protected virtual address mode. The 80286 also introduced additional instructions for memory management and protection compared to earlier Intel processors.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
The document summarizes the Intel 80386 microprocessor, which was introduced in 1985. It discusses the key features and architecture of both the 80386DX and 80386SX versions. The 80386 was Intel's first 32-bit microprocessor and supported addressing up to 4GB of physical memory and 64TB of virtual memory using segmentation and paging. It had several operating modes and instruction sets to support multitasking and memory protection in protected mode.
The document discusses the input/output system of the Intel 80386 microprocessor. It has the following key points:
1. The 80386 I/O system is similar to previous Intel 8086 processors, with 64K bytes of I/O space available. Memory mapped I/O can also be implemented to access up to 4GB of I/O locations.
2. New features in the 80386 include I/O privilege information added to the task state segment for protected mode. I/O locations can also be blocked in protected mode to prohibit access.
3. Memory and I/O are controlled separately, with different control signals for reads and writes. Timing diagrams show the non-p
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
The document provides information on the architecture of the 8086 microprocessor. It describes the Execution Unit (EU) and Bus Interface Unit (BIU) that partition the CPU logic. The EU is responsible for executing instructions while the BIU handles fetching instructions and operands from memory. The EU contains an ALU, registers including general purpose, segment, pointer and index registers, and a flag register. It also describes the various addressing modes supported by the 8086.
The document discusses the Universal Synchronous Asynchronous Receiver Transmitter (USART) which is a serial communication device. It describes the USART's synchronous and asynchronous communication modes and includes a block diagram and explanation of its transmitter, receiver, and pin sections. The USART receives parallel data from a microprocessor and transmits it serially or vice versa while including start/stop bits and potentially parity bits. It was commonly used to connect two microprocessor systems or for modem interfacing.
An 8086-based microcomputer system consists of the following components: 8086 CPU, ROM, RAM, peripherals, control bus, address bus, and data bus. The buses include the control bus which outputs signals like M/IO, RD, WR. The address and data buses are multiplexed and use latches to separate the address and data. The system also includes transceivers, a clock generator, and interrupt and DMA controllers. The 8086 can operate in minimum or maximum mode, with different control signal outputs in each mode. Read and write cycles take 4 clock cycles each and involve latching the address, then transferring/accepting the data.
8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. In April 1978, intel introduced this microprocessor and it was officially released on June 8.
PAI Unit 2 Segmentation in 80386 microprocessorKanchanPatil34
2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers types of address spaces : Logical, linear, Physical, Address Translation in 80386, Segment Descriptor Format, Types of Segment Descriptors,
The document discusses the memory organization and registers of the 8051 microcontroller. It describes the program memory and data memory, which are implemented using EPROM and RAM respectively. It then discusses the different registers of the 8051 including the accumulator, B register, data pointer register, stack pointer register, and special function registers. The special function registers are used for tasks like timer control and interrupt control.
The 8237 DMA controller allows data transfer between I/O devices and memory without CPU intervention. It uses HOLD and HLDA signals to request and acknowledge DMA actions from the CPU. The 8237 contains registers like CAR, CWCR, CR, and SR to program DMA channel operations, addresses, counts, and status. It can perform DMA transfers at up to 1.6 MB/s across 4 channels. Modern systems integrate DMA controllers within chipsets rather than using discrete 8237 components.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has two main components: the Bus Interface Unit (BIU) handles bus operations like instruction fetching and memory access, while the Execution Unit (EU) decodes and executes instructions. The BIU contains registers for the code, data, extra, and stack segments as well as an instruction queue. The EU has registers for accumulation, base, count, data, pointers, and flags, and contains an ALU and decoder. It executes instructions from the queued bytes using a pipeline architecture.
The document discusses the registers of the 80386 microprocessor. It describes:
1) The 80386 has eight 32-bit general purpose registers (EAX, EBX, ECX, EDX, EBP, ESP, ESI, EDI) that can be used as either 8-bit or 16-bit registers. It also has six segment registers (CS, SS, DS, ES, FS, GS).
2) The 80386 has additional registers compared to the 8086, including a 32-bit instruction pointer (EIP), status flags register (EFLAGS), and two additional segment registers (FS and GS).
3) The document provides details on the various status flags in
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
The document discusses the minimum and maximum mode systems of the 8086 microprocessor. In minimum mode, the 8086 generates all control signals and a single processor is used. In maximum mode, an external bus controller chip generates control signals and multiple processors can be used. It describes the components, address latching, read and write cycles, and I/O interfacing for both minimum and maximum mode 8086 systems.
The microprocessor is a chip that processes data using built-in transistors and cache. Microprocessors come in different types like CISC and RISC based on the number of instructions. Intel Pentium microprocessors power everyday applications while Intel Celeron microprocessors are more economical. Microprocessors connect to the motherboard via different sockets and slots and can be configured, upgraded, and troubleshot.
Register Organization of 8086, Architecture, Signal Description of 8086, Physical Memory
Organization, General Bus Operation, I/O Addressing Capability, Special Processor Activities,
Minimum Mode 8086 System and Timings, Maximum Mode 8086 System and Timings.
Addressing Modes of 8086.
The document describes the architecture and features of the 8086 microprocessor. It is a 16-bit microprocessor that has a 20-bit address bus allowing it to access up to 1MB of memory. It has two main units - the Bus Interface Unit (BIU) which handles bus operations like instruction fetching, and the Execution Unit (EU) which decodes and executes instructions. The BIU and EU operate asynchronously, allowing for pipelined execution to improve performance. The 8086 can operate in minimum or maximum mode depending on the state of the MN/MX pin.
The document describes the architecture and features of the 8086 microprocessor. It is a 16-bit microprocessor that has a 20-bit address bus allowing it to access up to 1MB of memory. It has two main units - the Bus Interface Unit (BIU) which handles bus operations like instruction fetching, and the Execution Unit (EU) which decodes and executes instructions. The BIU and EU operate asynchronously, allowing for pipelined execution to improve performance. The 8086 can operate in minimum or maximum mode depending on the state of the MN/MX pin.
The document provides information on the architecture of the 8086 microprocessor. It describes the Execution Unit (EU) and Bus Interface Unit (BIU) that partition the CPU logic. The EU is responsible for executing instructions while the BIU handles fetching instructions and operands from memory. The EU contains an ALU, registers including general purpose, segment, pointer and index registers, and a flag register. It also describes the various addressing modes supported by the 8086.
The document discusses the Universal Synchronous Asynchronous Receiver Transmitter (USART) which is a serial communication device. It describes the USART's synchronous and asynchronous communication modes and includes a block diagram and explanation of its transmitter, receiver, and pin sections. The USART receives parallel data from a microprocessor and transmits it serially or vice versa while including start/stop bits and potentially parity bits. It was commonly used to connect two microprocessor systems or for modem interfacing.
An 8086-based microcomputer system consists of the following components: 8086 CPU, ROM, RAM, peripherals, control bus, address bus, and data bus. The buses include the control bus which outputs signals like M/IO, RD, WR. The address and data buses are multiplexed and use latches to separate the address and data. The system also includes transceivers, a clock generator, and interrupt and DMA controllers. The 8086 can operate in minimum or maximum mode, with different control signal outputs in each mode. Read and write cycles take 4 clock cycles each and involve latching the address, then transferring/accepting the data.
8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. In April 1978, intel introduced this microprocessor and it was officially released on June 8.
PAI Unit 2 Segmentation in 80386 microprocessorKanchanPatil34
2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers types of address spaces : Logical, linear, Physical, Address Translation in 80386, Segment Descriptor Format, Types of Segment Descriptors,
The document discusses the memory organization and registers of the 8051 microcontroller. It describes the program memory and data memory, which are implemented using EPROM and RAM respectively. It then discusses the different registers of the 8051 including the accumulator, B register, data pointer register, stack pointer register, and special function registers. The special function registers are used for tasks like timer control and interrupt control.
The 8237 DMA controller allows data transfer between I/O devices and memory without CPU intervention. It uses HOLD and HLDA signals to request and acknowledge DMA actions from the CPU. The 8237 contains registers like CAR, CWCR, CR, and SR to program DMA channel operations, addresses, counts, and status. It can perform DMA transfers at up to 1.6 MB/s across 4 channels. Modern systems integrate DMA controllers within chipsets rather than using discrete 8237 components.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has two main components: the Bus Interface Unit (BIU) handles bus operations like instruction fetching and memory access, while the Execution Unit (EU) decodes and executes instructions. The BIU contains registers for the code, data, extra, and stack segments as well as an instruction queue. The EU has registers for accumulation, base, count, data, pointers, and flags, and contains an ALU and decoder. It executes instructions from the queued bytes using a pipeline architecture.
The document discusses the registers of the 80386 microprocessor. It describes:
1) The 80386 has eight 32-bit general purpose registers (EAX, EBX, ECX, EDX, EBP, ESP, ESI, EDI) that can be used as either 8-bit or 16-bit registers. It also has six segment registers (CS, SS, DS, ES, FS, GS).
2) The 80386 has additional registers compared to the 8086, including a 32-bit instruction pointer (EIP), status flags register (EFLAGS), and two additional segment registers (FS and GS).
3) The document provides details on the various status flags in
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
The document discusses the minimum and maximum mode systems of the 8086 microprocessor. In minimum mode, the 8086 generates all control signals and a single processor is used. In maximum mode, an external bus controller chip generates control signals and multiple processors can be used. It describes the components, address latching, read and write cycles, and I/O interfacing for both minimum and maximum mode 8086 systems.
The microprocessor is a chip that processes data using built-in transistors and cache. Microprocessors come in different types like CISC and RISC based on the number of instructions. Intel Pentium microprocessors power everyday applications while Intel Celeron microprocessors are more economical. Microprocessors connect to the motherboard via different sockets and slots and can be configured, upgraded, and troubleshot.
Register Organization of 8086, Architecture, Signal Description of 8086, Physical Memory
Organization, General Bus Operation, I/O Addressing Capability, Special Processor Activities,
Minimum Mode 8086 System and Timings, Maximum Mode 8086 System and Timings.
Addressing Modes of 8086.
The document describes the architecture and features of the 8086 microprocessor. It is a 16-bit microprocessor that has a 20-bit address bus allowing it to access up to 1MB of memory. It has two main units - the Bus Interface Unit (BIU) which handles bus operations like instruction fetching, and the Execution Unit (EU) which decodes and executes instructions. The BIU and EU operate asynchronously, allowing for pipelined execution to improve performance. The 8086 can operate in minimum or maximum mode depending on the state of the MN/MX pin.
The document describes the architecture and features of the 8086 microprocessor. It is a 16-bit microprocessor that has a 20-bit address bus allowing it to access up to 1MB of memory. It has two main units - the Bus Interface Unit (BIU) which handles bus operations like instruction fetching, and the Execution Unit (EU) which decodes and executes instructions. The BIU and EU operate asynchronously, allowing for pipelined execution to improve performance. The 8086 can operate in minimum or maximum mode depending on the state of the MN/MX pin.
The document describes the architecture and features of the 8086 microprocessor. It is a 16-bit microprocessor that has a 20-bit address bus allowing it to access up to 1MB of memory. It has two main units - the Bus Interface Unit (BIU) which handles bus operations like instruction fetching, and the Execution Unit (EU) which decodes and executes instructions. The BIU and EU operate asynchronously, allowing for pipelined execution to improve performance. The 8086 can operate in minimum or maximum mode depending on the state of the MN/MX pin.
The document provides details about the 8086 microprocessor architecture. Some key points:
- The 8086 is a 16-bit microprocessor that can access up to 1MB of memory using a 20-bit address bus and supports up to 64K I/O ports.
- It has an internal architecture divided into a Bus Interface Unit (BIU) and Execution Unit (EU) that allows for overlapping of instruction fetching and execution via pipelining.
- The BIU handles external bus operations like instruction fetching and memory/I/O access. The EU decodes and executes instructions, performing operations on operands retrieved by the BIU.
The document summarizes key details about the 8086 microprocessor:
1. It has 29,000 transistors and is housed in a 40-pin DIP package.
2. It can operate in two modes - MIN mode for a single processor system and MAX mode for a multiprocessor system.
3. It has separate execution and bus interface units that allow parallel processing for improved performance over the 8085.
The document discusses the 8086 microprocessor. It provides details about the pin diagram of 8086 in minimum and maximum modes. It mentions that 8086 is manufactured using HMOS technology and has approximately 29,000 transistors housed in a 40-pin DIP package. It can operate in two modes - minimum and maximum mode based on the state of the MN/MX pin. The minimum mode is for a uniprocessor system while maximum mode is for a multiprocessor system.
The document provides information about microprocessors and the Intel 8086 microprocessor. It discusses the following:
- The functional blocks and registers of a typical microprocessor.
- An overview of the Intel 8086 including its introduction in 1978, transistor count, and operating modes.
- The pins and signals of the 8086 including address, data, control signals and minimum/maximum mode signals.
- The architecture of the 8086 including its bus interface unit, execution unit, registers, memory organization using segments and offsets, and addressing modes.
The 8086 microprocessor is Intel's first 16-bit microprocessor released in 1978. It has 20 address lines allowing it to access up to 1 megabyte of memory. It uses segmented memory architecture where the 1 megabyte address space is divided into segments of 64KB each. The 8086 has four 16-bit segment registers - code segment, data segment, stack segment, and extra segment. It operates on minimum and maximum modes determined by the MN/MX pin. In maximum mode, additional pins are used for bus requests and grants.
The document summarizes the internal architecture of the 8086 microprocessor. It has two main units: the Bus Interface Unit (BIU) which handles bus operations like instruction fetching and memory access, and the Execution Unit (EU) which decodes and executes instructions. The BIU uses an instruction queue to implement pipelining for overlapping fetch and execution. It also generates physical addresses by combining segment registers and offset addresses. The EU contains an ALU and flag register. Memory is organized into segments addressed using segment registers. Pipelining improves performance by allowing parallel fetch, decode, and execute operations.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
The document describes the minimum mode interface of the 8086 microprocessor. It discusses the various signals that are provided by the 8086 to implement the memory and I/O interface in minimum mode. This includes the address/data bus lines, status signals, control signals, interrupt signals, and DMA interface signals. The address/data bus is multiplexed and used for both addresses and data. Status, control and interrupt signals help indicate the type of bus cycle and transfer direction. The DMA interface uses HOLD and HLDA signals to allow external devices to gain control of the bus.
The 8086 microprocessor is a 16-bit processor introduced by Intel in 1978. It has a 16-bit data bus and 20-bit address bus, allowing it to access up to 1MB of memory. The 8086 has an internal architecture divided into a Bus Interface Unit and an Execution Unit that can work simultaneously. The BIU handles external bus operations like fetching instructions and data from memory, while the EU decodes instructions and performs arithmetic/logical operations. The 8086 supports memory segmentation through the use of segment registers and pointers to generate 20-bit physical addresses.
This document provides an overview of the 8086 microprocessor, including its functional blocks, generations, pins and signals, architecture, and registers. Some key points:
- The 8086 was Intel's first 16-bit microprocessor released in 1978. It had 29,000 transistors and could access up to 1MB of memory.
- It has a bus interface unit that fetches instructions and data from memory and handles addressing, and an execution unit that decodes and executes instructions.
- The architecture uses segment registers to access different segments of memory and pointers to determine instruction and data locations.
- The registers include general purpose, pointer, index, flag and instruction registers that support various operations.
The 8086 microprocessor is Intel's first 16-bit microprocessor released in 1978. It has approximately 29,000 transistors, operates at 5V, and can address up to 1 megabyte of memory space through its 20-bit address bus. The 8086 uses separate 16-bit address spaces for memory and I/O devices and can operate in minimum or maximum modes depending on the state of its MN/MX pin. It has an execution unit that performs arithmetic and logic operations and a bus interface unit that fetches instructions and data from memory and I/O ports.
The 8086 is a 16-bit microprocessor introduced by Intel in 1978. It has a 16-bit external data bus and 20-bit address bus, can access up to 1 MB of memory, and has 14 general purpose 16-bit registers. The 8086 architecture consists of a Bus Interface Unit which handles memory access and I/O, and an Execution Unit which decodes and executes instructions. It supports two operating modes - minimum and maximum - which determine clock speed and timing.
The document provides an overview of the 8086 microprocessor, which was Intel's first 16-bit microprocessor released in 1978. It describes the five generations of microprocessors leading up to the 8086. It then discusses the functional blocks, pins and signals, architecture, and registers of the 8086 microprocessor. The 8086 used a 20-bit address bus to access up to 1MB of memory. It had four 16-bit segment registers to access different segments of memory and used multiplexed address and data lines to reduce the number of pins.
The 8086 architecture introduced Intel's first 16-bit microprocessor. It uses a 40-pin IC with an n-channel depletion mode silicon gate technology. The CPU logic is divided into an Execution Unit and Bus Interface Unit. The BIU interfaces with the external bus and executes bus operations, fetching instructions from memory and passing them to the EU. The EU then executes the instructions, manipulating registers and flags. The 8086 has 14 registers including data, segment, pointer, index, program counter, and flag registers.
The 8086 processor has a 16-bit data bus and 20-bit address bus. It uses a multiplexed address/data bus design that reduces pins but slows data transfer. It has separate bus interface and execution units that allow instruction fetching and execution to overlap via an instruction queue. The bus interface unit handles memory and I/O access while the execution unit performs arithmetic/logical operations. In certain conditions like memory access or jumps, the execution unit must wait idle for the next instruction. The main difference between the 8086 and 8088 is the 8-bit data bus of the 8088, making it around 30% slower.
Teradata Corporation is an American company that sells data warehousing hardware and software. It was founded in 1979 and spun off from NCR Corporation in 2007. Teradata's products include integrated data warehouse appliances and software that allow customers to consolidate data from various sources and perform analysis. The company has over 10,000 employees and annual revenue of over $2.6 billion.
Teradata is an American company that sells analytic data platforms and related services. It was originally a division of NCR Corporation but spun off in 2007. Teradata's products consolidate data from different sources and make it available for analysis. It uses a massively parallel processing architecture that allows for linear scalability. Major customers include Walmart, AT&T, and Continental Airlines. Teradata competes with other data warehousing solutions from Oracle, IBM, and Microsoft.
The document discusses Linux/Unix interview questions and answers. It covers topics such as the GRUB bootloader, the Linux boot process, user profile files, changing the default runlevel, displaying user information with the finger command, inode numbers, increasing disk read performance, password expiration times, locking user passwords, default shells, user attributes defined in /etc/login.defs, changing the system's authentication method, modifying file attributes with chattr, network interface configuration files, changing network interface settings, the DNS configuration file, exporting NFS directories, checking open ports, soft vs hard links, setting expired passwords, restricting file insertion, displaying or killing processes accessing files/folders, killing all processes for a user, daily system analysis reports
Linux was created by Linus Torvalds in 1991 based on UNIX. It is an open source operating system with a modular design consisting of the kernel at the core which manages memory, processes, and hardware access. The shell provides a command line interface between users and the kernel while the file system arranges files in a hierarchical structure with everything treated as a file. Common directories include /bin, /sbin, /etc, /dev, /proc, /var, /tmp, /usr, /home, and help is available through man pages or command --help.
Linux Crontab allows scheduling routine jobs to run automatically in the background at specific times or days. The document provides 15 examples of cron job configurations, including running jobs daily, weekly, monthly, at startup or reboot, and during specific time ranges. It also covers viewing, editing, and installing cron jobs, as well as redirecting output and specifying environment variables. Anacron is introduced as an alternative for machines that may not be running 24/7, to better ensure scheduled jobs run as expected.
This document provides an overview of basic Linux commands for navigation, listing directories, reading and manipulating files. It explains commands like pwd, cd, ls, cat, cp, mv, rm, mkdir to change directories, list files, read files, copy, move and delete files/directories. It also introduces the vi editor for creating new files and mentions some other miscellaneous commands like date, chmod, user management tools.
The kernel is the central component of most computer operating systems. It acts as a bridge between applications and hardware, managing system resources and communication. Kernels can be categorized as monolithic, micro, hybrid, or exokernel based on how operating system services are implemented. A monolithic kernel executes all services together, while a microkernel runs most in user space for modularity. Hybrid kernels combine aspects of both.
To install Red Hat Enterprise Linux 6 (RHEL 6), insert the installation DVD and boot the system. The graphical installer will launch and guide you through the installation process. This includes selecting packages, partitioning disks, setting the timezone and root password. Once installed, additional configuration steps like software updates and user account creation are completed.
This document provides a tutorial on common Linux commands. It lists commands like ls to list files, file to check file types, mkdir to make directories, cd to change directories, cp to copy, mv to move, and rm to remove files and directories. It also covers commands like cat to view file contents, grep to search files, more and less to page through large files, chown to change ownership, chmod to change permissions, ps to view processes, and kill and killall to terminate processes. The document explains that running "man [command]" provides documentation for each command.
A monolithic kernel runs all operating system services and device drivers in the kernel space of memory. This provides rich hardware access but dependencies between system components mean a bug can crash the entire system. A microkernel moves most OS services like networking and filesystems into userspace processes or "servers" that communicate through a minimal kernel. This improves modularity and stability but incurs more overhead from frequent context switches between user and kernel mode.
This document provides a summary of common Linux commands organized into the following sections: setting kernel parameters, setting process limits, adding interim swap/tmp space, troubleshooting tools, Bash shell tweaks, key system configuration files, system information commands, network information commands, package management commands, user management commands, backup/restore/file transfer commands, and miscellaneous commands. It includes brief descriptions of commands such as lsof, netstat, tcpdump, strace, chage, passwd, tar, zip, and others. The document is a pocket guide to essential Linux commands and system configuration.
This document provides 50 examples of common Linux/Unix commands along with brief explanations and usage examples for each command. Some of the commands highlighted include tar, grep, find, ssh, sed, awk, vim, diff, sort, export, xargs, ls, pwd, cd, gzip, bzip2, unzip, shutdown, ftp, crontab, service, ps, top, df, kill, rm, cp, mv, cat, mount, chmod, chown, passwd, mkdir, ifconfig, and uname. The document is intended to give readers a quick start on frequently used commands.
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25 most frequently used linux ip tables rules examplesTeja Bheemanapally
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LF Energy Webinar: Carbon Data Specifications: Mechanisms to Improve Data Acc...DanBrown980551
This LF Energy webinar took place June 20, 2024. It featured:
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In response to the urgency and scale required to effectively address climate change, open source solutions offer significant potential for driving innovation and progress. Currently, there is a growing demand for standardization and interoperability in energy data and modeling. Open source standards and specifications within the energy sector can also alleviate challenges associated with data fragmentation, transparency, and accessibility. At the same time, it is crucial to consider privacy and security concerns throughout the development of open source platforms.
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Day 4 - Excel Automation and Data ManipulationUiPathCommunity
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8086 microprocessor
1. 8086 Microprocessor (cont..)
• It is a 16 bit µp.
• 8086 has a 20 bit address bus can access upto 220 memory
locations ( 1 MB) .
• It can support upto 64K I/O ports.
• It provides 14, 16-bit registers.
• It has multiplexed address and data bus AD0- AD15
and A16 – A19.
M. Krishna Kumar
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2. 8086 Microprocessor (cont..)
• It requires single phase clock with 33% duty cycle to
provide internal timing.
• 8086 is designed to operate in two modes, Minimum and
Maximum.
• It can prefetches upto 6 instruction bytes from memory and
queues them in order to speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
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3. 8086 Microprocessor (cont..)
Minimum and Maximum Modes:
• The minimum mode is selected by applying logic 1 to the
MN / MX# input pin. This is a single microprocessor
configuration.
•
The maximum mode is selected by applying logic 0 to the
MN / MX# input pin. This is a multi micro processors
configuration.
M. Krishna Kumar
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4. 8086 Microprocessor (cont..)
AH
BL
CH
GENERAL
REGISTERS
AL
BH
CL
DH
DL
ADDRESS BUS
∑
( 20 )
BITS
SP
DATA BUS
BP
( 16 )
BITS
SI
DI
ES
CS
SS
DS
ALU DATA BUS
IP
8
16 BITS
0
BUS
6
CONTROL
LOGIC
B
U
S
TEMPORARY REGISTERS
EU
CONTROL
Q BUS
SYSTEM
ALU
INSTRUCTION QUEUE
1
2
3
4
5
6
8 BIT
FLAGS
BUS INTERFACE UNIT
( BIU)
EXECUTION UNIT ( EU )
Fig:
M. Krishna Kumar
8
MM/M1/LU3/V1/2004
4
6. VCC
GND
A0 - A15, A16 / S3 – A19/S6
INTR
_____
INTA
ADDRESS / DATA BUS
INTERRUPT
______
INTERFACE
TEST
NMI
D0 - D15
8086
ALE
___
MPU
RESET
BHE / S7
__
HOLD
INTERFACE
M / IO
CONTROLS
DMA
HLDA
MEMORY
I/O
RD
MN / MX
DT / R
_____
WR
VCC
____
____
__
_____
DEN
MODE
SELECT
READY
CLK
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7. Internal Architecture of 8086
• 8086 has two blocks BIU and EU.
• The BIU performs all bus operations such as instruction
fetching, reading and writing operands for memory and
calculating the addresses of the memory operands.
• The instruction bytes are transferred to the instruction
queue.
• EU executes instructions from the instruction system byte
queue.
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8. Internal Architecture of 8086 (cont..)
• Both units operate asynchronously to give the 8086 an
overlapping instruction fetch and execution mechanism
which is called as Pipelining. This results in efficient use
of the system bus and system performance.
• BIU contains Instruction queue, Segment registers,
Instruction pointer, Address adder.
• EU contains Control circuitry, Instruction decoder, ALU,
Pointer and Index register, Flag register.
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9. Internal Architecture of 8086 (cont..)
• Bus Interfacr Unit:
• It provides a full 16 bit bidirectional data bus and 20 bit
address bus.
• The bus interface unit is responsible for performing all
external bus operations.
Specifically it has the following functions:
• Instruction fetch, Instruction queuing, Operand fetch and
storage, Address relocation and Bus control.
• The BIU uses a mechanism known as an instruction stream
queue to implement a pipeline architecture.
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10. Internal Architecture of 8086 (cont..)
• This queue permits prefetch of up to six bytes of
instruction code. When ever the queue of the BIU is not
full, it has room for at least two more bytes and at the same
time the EU is not requesting it to read or write operands
from memory, the BIU is free to look ahead in the program
by prefetching the next sequential instruction.
• These prefetching instructions are held in its FIFO queue.
With its 16 bit data bus, the BIU fetches two instruction
bytes in a single memory cycle.
• After a byte is loaded at the input end of the queue, it
automatically shifts up through the FIFO to the empty
location nearest the output.
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11. Internal Architecture of 8086 (cont..)
• The EU accesses the queue from the output end. It reads
one instruction byte after the other from the output of the
queue. If the queue is full and the EU is not requesting
access to operand in memory.
• These intervals of no bus activity, which may occur
between bus cycles are known as Idle state.
• If the BIU is already in the process of fetching an
instruction when the EU request it to read or write
operands from memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating the operand
read / write cycle.
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12. Internal Architecture of 8086 (cont..)
• The BIU also contains a dedicated adder which is used to
generate the 20 bit physical address that is output on the
address bus. This address is formed by adding an appended
16 bit segment address and a 16 bit offset address.
• For example, the physical address of the next instruction to
be fetched is formed by combining the current contents of
the code segment CS register and the current contents of
the instruction pointer IP register.
• The BIU is also responsible for generating bus control
signals such as those for memory read or write and I/O
read or write.
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13. Internal Architecture of 8086 (cont..)
• EXECUTION UNIT : The Execution unit is responsible
for decoding and executing all instructions.
• The EU extracts instructions from the top of the queue in
the BIU, decodes them, generates operands if necessary,
passes them to the BIU and requests it to perform the read
or write bys cycles to memory or I/O and perform the
operation specified by the instruction on the operands.
• During the execution of the instruction, the EU tests the
status and control flags and updates them based on the
results of executing the instruction.
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14. Internal Architecture of 8086 (cont..)
• If the queue is empty, the EU waits for the next instruction
byte to be fetched and shifted to top of the queue.
• When the EU executes a branch or jump instruction, it
transfers control to a location corresponding to another set
of sequential instructions.
• Whenever this happens, the BIU automatically resets the
queue and then begins to fetch instructions from this new
location to refill the queue.
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15. Internal Architecture of 8086 (cont..)
COMMON SIGNALS
Name
Function
AD 15 – AD 0
A19 / S 6 – A 16 / S 3
Address/ Data Bus
BHE
/S7
MN / MX
RD
Address / Status
Bus High Enable /
Status
Minimum /
Maximum Mode
Control
Read Control
Type
Bidirectional
3 - state
Output 3 - State
Output
3- State
Input
Output 3- State
TEST
Wait On Test Control
Input
READY
Wait State Controls
Input
RESET
NMI
INTR
CLK
Vcc
GND
M. Krishna Kumar
System Reset
Non - Maskable
Interrupt Request
Interrupt Request
System Clock
+ 5V
Ground
MM/M1/LU3/V1/2004
Input
Input
Input
Input
Input
15
16. Internal Architecture of 8086 (cont..)
Minimum Mode Signals
Name
HOLD
HLDA
( MN/ MX = Vcc )
Function
Hold Request
Hold Acknowledge
Type
Input
Output
WR
Write Control
Output
,
3- state
-
M/IO
Memory or IO Control
,
Output
3-State
,
Output
3- State
DT/R
Data Transmit /
Receiver
DEN
Date Enable
Output
,
3-State
ALE
Address Latch Enable
Output
INTA
M. Krishna Kumar
Interrupt Acknowledge
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Output
16
17. Internal Architecture of 8086 (cont..)
Maximum mode signals ( MN / MX = GND )
Name
RQ / GT1, 0
LOCK
S2 – S0
QS1, QS0
M. Krishna Kumar
Function
Type
Request / Grant Bus
Access Control
Bidirectional
Bus Priority Lock Control
Output,
3- State
Bus Cycle Status
Output,
3- State
Instruction Queue Status
MM/M1/LU3/V1/2004
Output
17
18. Minimum Mode Interface
• When the Minimum mode operation is selected, the 8086
provides all control signals needed to implement the
memory and I/O interface.
• The minimum mode signal can be divided into the
following basic groups : address/data bus, status, control,
interrupt and DMA.
• Address/Data Bus : these lines serve two functions. As an
address bus is 20 bits long and consists of signal lines A0
through A19. A19 represents the MSB and A0 LSB. A 20bit
address gives the 8086 a 1Mbyte memory address space.
More over it has an independent I/O address space which
is 64K bytes in length.
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19. Minimum Mode Interface ( cont..)
• The 16 data bus lines D0 through D15 are actually
multiplexed with address lines A0 through A15
respectively. By multiplexed we mean that the bus work as
an address bus during first machine cycle and as a data bus
during next machine cycles. D15 is the MSB and D0 LSB.
• When acting as a data bus, they carry read/write data for
memory, input/output data for I/O devices, and interrupt
type codes from an interrupt controller.
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20. Minimum Mode Interface ( cont..)
Vcc
GND
INTR
A0-A15,A16/S3 – A19/S6
INTA
Interrupt
interface
Address / data bus
TEST
D0 – D15
NMI
8086
RESET
MPU
ALE
BHE / S7
M / IO
HOLD
DMA
interface
DT / R
Memory
I/O controls
RD
HLDA
WR
Vcc
DEN
Mode select
READY
MN / MX
CLK clock
Block Diagram of the Minimum Mode 8086 MPU
MM/M1/LU3/V1/2004
M. Krishna Kumar
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21. Minimum Mode Interface ( cont..)
• Status signal : The four most significant address lines A19
through A16 are also multiplexed but in this case with
status signals S6 through S3. These status bits are output on
the bus at the same time that data are transferred over the
other bus lines.
• Bit S4 and S3 together from a 2 bit binary code that
identifies which of the 8086 internal segment registers are
used to generate the physical address that was output on
the address bus during the current bus cycle.
• Code S4S3 = 00 identifies a register known as extra
segment register as the source of the segment address.
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22. Minimum Mode Interface ( cont..)
S4
S3
Segment Register
0
0
Extra
0
1
Stack
1
0
Code / none
1
1
Data
Memory segment status codes.
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23. Minimum Mode Interface ( cont..)
• Status line S5 reflects the status of another internal
characteristic of the 8086. It is the logic level of the
internal enable flag. The last status bit S6 is always at the
logic 0 level.
• Control Signals : The control signals are provided to
support the 8086 memory I/O interfaces. They control
functions such as when the bus is to carry a valid address
in which direction data are to be transferred over the bus,
when valid write data are on the bus and when to put read
data on the system bus.
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24. Minimum Mode Interface ( cont..)
• ALE is a pulse to logic 1 that signals external circuitry
when a valid address word is on the bus. This address must
be latched in external circuitry on the 1-to-0 edge of the
pulse at ALE.
• Another control signal that is produced during the bus
cycle is BHE bank high enable. Logic 0 on this used as a
memory enable signal for the most significant byte half of
the data bus D8 through D1. These lines also serves a
second function, which is as the S7 status line.
• Using the M/IO and DT/R lines, the 8086 signals which
type of bus cycle is in progress and in which direction data
are to be transferred over the bus.
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25. Minimum Mode Interface ( cont..)
• The logic level of M/IO tells external circuitry whether a
memory or I/O transfer is taking place over the bus. Logic
1 at this output signals a memory operation and logic 0 an
I/O operation.
• The direction of data transfer over the bus is signaled by
the logic level output at DT/R. When this line is logic 1
during the data transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either written into
memory or output to an I/O device.
• On the other hand, logic 0 at DT/R signals that the bus is in
the receive mode. This corresponds to reading data from
memory or input of data from an input port.
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26. Minimum Mode Interface ( cont..)
• The signal read RD and write WR indicates that a read bus
cycle or a write bus cycle is in progress. The 8086 switches
WR to logic 0 to signal external device that valid write or
output data are on the bus.
• On the other hand, RD indicates that the 8086 is
performing a read of data of the bus. During read
operations, one other control signal is also supplied. This is
DEN ( data enable) and it signals external devices when
they should put data on the bus.
• There is one other control signal that is involved with the
memory and I/O interface. This is the READY signal.
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27. Minimum Mode Interface ( cont..)
• READY signal is used to insert wait states into the bus
cycle such that it is extended by a number of clock periods.
This signal is provided by an external clock generator
device and can be supplied by the memory or I/O subsystem to signal the 8086 when they are ready to permit
the data transfer to be completed.
• Interrupt signals : The key interrupt interface signals are
interrupt request (INTR) and interrupt acknowledge
( INTA).
• INTR is an input to the 8086 that can be used by an
external device to signal that it need to be serviced.
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28. Minimum Mode Interface ( cont..)
• Logic 1 at INTR represents an active interrupt request.
When an interrupt request has been recognized by the
8086, it indicates this fact to external circuit with pulse to
logic 0 at the INTA output.
• The TEST input is also related to the external interrupt
interface. Execution of a WAIT instruction causes the 8086
to check the logic level at the TEST input.
• If the logic 1 is found, the MPU suspend operation and
goes into the idle state. The 8086 no longer executes
instructions, instead it repeatedly checks the logic level of
the TEST input waiting for its transition back to logic 0.
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29. Minimum Mode Interface ( cont..)
• As TEST switches to 0, execution resume with the next
instruction in the program. This feature can be used to
synchronize the operation of the 8086 to an event in
external hardware.
• There are two more inputs in the interrupt interface: the
nonmaskable interrupt NMI and the reset interrupt RESET.
• On the 0-to-1 transition of NMI control is passed to a
nonmaskable interrupt service routine. The RESET input is
used to provide a hardware reset for the 8086. Switching
RESET to logic 0 initializes the internal register of the
8086 and initiates a reset service routine.
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30. Minimum Mode Interface.
• DMA Interface signals :The direct memory access DMA
interface of the 8086 minimum mode consist of the HOLD
and HLDA signals.
• When an external device wants to take control of the
system bus, it signals to the 8086 by switching HOLD to
the logic 1 level. At the completion of the current bus
cycle, the 8086 enters the hold state. In the hold state,
signal lines AD0 through AD15, A16/S3 through A19/S6,
BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the
high Z state. The 8086 signals external device that it is in
this state by switching its HLDA output to logic 1 level.
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31. Maximum Mode Interface
• When the 8086 is set for the maximum-mode
configuration, it provides signals for implementing a
multiprocessor / coprocessor system environment.
• By multiprocessor environment we mean that one
microprocessor exists in the system and that each
processor is executing its own program.
• Usually in this type of system environment, there are
some system resources that are common to all processors.
• They are called as global resources. There are also other
resources that are assigned to specific processors. These
are known as local or private resources.
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32. Maximum Mode Interface (cont..)
• Coprocessor also means that there is a second processor in
the system. In this two processor does not access the bus at
the same time.
• One passes the control of the system bus to the other and
then may suspend its operation.
• In the maximum-mode 8086 system, facilities are provided
for implementing allocation of global resources and
passing bus control to other microprocessor or
coprocessor.
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34. Maximum Mode Interface (cont..)
• 8288 Bus Controller – Bus Command and Control
Signals: 8086 does not directly provide all the signals that
are required to control the memory, I/O and interrupt
interfaces.
• Specially the WR, M/IO, DT/R, DEN, ALE and INTA,
signals are no longer produced by the 8086. Instead it
outputs three status signals S0, S1, S2 prior to the initiation
of each bus cycle. This 3- bit bus status code identifies
which type of bus cycle is to follow.
• S2S1S0 are input to the external bus controller device, the
bus controller generates the appropriately timed command
and control signals.
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35. Maximum Mode Interface (cont..)
Status Inputs
CPU Cycles
S2
S1
S0
0
0
0
0
0
0
1
1
0
1
0
1
Interrupt Acknowledge
1
0
0
Instruction Fetch
1
0
1
Read Memory
1
1
1
0
Write Memory
1
1
Read I/O Port
Write I/O Port
Halt
Passive
8288
Command
INTA
IORC
IOWC, AIOWC
None
MRDC
MRDC
MWTC, AMWC
None
Bus Status Codes
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36. Maximum Mode Interface (cont..)
• The 8288 produces one or two of these eight command
signals for each bus cycles. For instance, when the 8086
outputs the code S2S1S0 equals 001, it indicates that an I/O
read cycle is to be performed.
• In the code 111 is output by the 8086, it is signaling that no
bus activity is to take place.
• The control outputs produced by the 8288 are DEN, DT/R
and ALE. These 3 signals provide the same functions as
those described for the minimum system mode. This set of
bus commands and control signals is compatible with the
Multibus and industry standard for interfacing
microprocessor systems.
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37. Maximum Mode Interface (cont..)
• 8289 Bus Arbiter – Bus Arbitration and Lock Signals :
This device permits processors to reside on the system bus.
It does this by implementing the Multibus arbitration
protocol in an 8086-based system.
• Addition of the 8288 bus controller and 8289 bus arbiter
frees a number of the 8086 pins for use to produce control
signals that are needed to support multiple processors.
• Bus priority lock ( LOCK) is one of these signals. It is
input to the bus arbiter together with status signals S0
through S2.
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38. Maximum Mode Interface (cont..)
• The output of 8289 are bus arbitration signals: bus busy
(BUSY), common bus request (CBRQ), bus priority out
(BPRO), bus priority in (BPRN), bus request (BREQ) and
bus clock (BCLK).
• They correspond to the bus exchange signals of the
Multibus and are used to lock other processor off the
system bus during the execution of an instruction by the
8086.
• In this way the processor can be assured of uninterrupted
access to common system resources such as global
memory.
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39. Maximum Mode Interface (cont..)
• Queue Status Signals : Two new signals that are produced
by the 8086 in the maximum-mode system are queue status
outputs QS0 and QS1. Together they form a 2-bit queue
status code, QS1QS0.
• Following table shows the four different queue status.
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40. Maximum Mode Interface (cont..)
QS1
QS0
0 (low)
0
0
1
1 (high)
1
0
1
Queue Status
No Operation. During the last clock cycle, nothing was
taken from the queue.
First Byte. The byte taken from the queue was the first
byte of the instruction.
Queue Empty. The queue has been reinitialized as a result
of the execution of a transfer instruction.
Subsequent Byte. The byte taken from the queue was a
subsequent byte of the instruction.
Queue status codes
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41. Maximum Mode Interface (cont..)
• Local Bus Control Signal – Request / Grant Signals: In
a maximum mode configuration, the minimum mode
HOLD, HLDA interface is also changed. These two are
replaced by request/grant lines RQ/ GT0 and RQ/ GT1,
respectively. They provide a prioritized bus access
mechanism for accessing the local bus.
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42. Minimum Mode 8086 System
• In a minimum mode 8086 system, the microprocessor
8086 is operated in minimum mode by strapping its
MN/MX pin to logic 1.
• In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
• The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
Some type of chip selection logic may be required for
selecting memory or I/O devices, depending upon the
address map of the system.
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43. Minimum Mode 8086 System (cont..)
• Latches are generally buffered output D-type flip-flops like
74LS373 or 8282. They are used for separating the valid
address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
• Transreceivers are the bidirectional buffers and some times
they are called as data amplifiers. They are required to
separate the valid data from the time multiplexed
address/data signals.
• They are controlled by two signals namely, DEN and
DT/R.
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44. Minimum Mode 8086 System (cont..)
• The DEN signal indicates the direction of data, i.e. from or
to the processor. The system contains memory for the
monitor and users program storage.
• Usually, EPROM are used for monitor storage, while
RAM for users program storage. A system may contain I/O
devices.
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45. Minimum Mode 8086 System (cont..)
• The clock generator generates the clock from the crystal
oscillator and then shapes it and divides to make it more
precise so that it can be used as an accurate timing
reference for the system.
• The clock generator also synchronizes some external signal
with the system clock. The general system organisation is
as shown in below fig.
• It has 20 address lines and 16 data lines, the 8086 CPU
requires three octal address latches and two octal data
buffers for the complete address and data separation.
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46. Minimum Mode 8086 System (cont..)
• The working of the minimum mode configuration system
can be better described in terms of the timing diagrams
rather than qualitatively describing the operations.
• The opcode fetch and read cycles are similar. Hence the
timing diagram can be categorized in two parts, the first is
the timing diagram for read cycle and the second is the
timing diagram for write cycle.
• The read cycle begins in T1 with the assertion of address
latch enable (ALE) signal and also M / IO signal. During
the negative going edge of this signal, the valid address is
latched on the local bus.
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47. Minimum Mode 8086 System (cont..)
• The BHE and A0 signals address low, high or both bytes.
From T1 to T4 , the M/IO signal indicates a memory or I/O
operation.
• At T2, the address is removed from the local bus and is
sent to the output. The bus is then tristated. The read (RD)
control signal is also activated in T2.
• The read (RD) signal causes the address device to enable
its data bus drivers. After RD goes low, the valid data is
available on the data bus.
• The addressed device will drive the READY line high.
When the processor returns the read signal to high level,
the addressed device will again tristate its bus drivers.
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48. Minimum Mode 8086 System (cont..)
• A write cycle also begins with the assertion of ALE and
the emission of the address. The M/IO signal is again
asserted to indicate a memory or I/O operation. In T2, after
sending the address in T1, the processor sends the data to
be written to the addressed location.
• The data remains on the bus until middle of T4 state. The
WR becomes active at the beginning of T2 (unlike RD is
somewhat delayed in T2 to provide time for floating).
• The BHE and A0 signals are used to select the proper byte
or bytes of memory or I/O word to be read or write.
• The M/IO, RD and WR signals indicate the type of data
transfer as specified in table below.
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49. Minimum Mode 8086 System (cont..)
M / IO
RD
WR
0
0
1
0
1
1
1
0
1
0
1
0
Transfer Type
I / O read
I/O write
Memory read
Memory write
Data Transfer table
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50. Minimum Mode 8086 System (cont..)
Clk
T1
T2
T3
TW
T4
ALE
ADD / STATUS
ADD / DATA
BHE
A19 – A16
A15 – A0
S7 – S3
Bus reserved
for data in
D15 – D0
RD
DEN
DT / R
Read Cycle Timing Diagram for Minimum Mode
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51. Minimum Mode 8086 System (cont..)
T1
T2
T3
TW
T4
T1
Clk
ALE
ADD / STATUS
BHE
A19 – A16
S7 – S3
ADD / DATA
A15 – A0
Valid data D15 – D0
WR
DEN
DT / R
Write Cycle Timing Diagram for Minimum Mode
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52. Minimum Mode 8086 System (cont..)
• Hold Response sequence: The HOLD pin is checked at
leading edge of each clock pulse. If it is received active by
the processor before T4 of the previous cycle or during T1
state of the current cycle, the CPU activates HLDA in the
next clock cycle and for succeeding bus cycles, the bus
will be given to another requesting master.
• The control of the bus is not regained by the processor
until the requesting master does not drop the HOLD pin
low. When the request is dropped by the requesting master,
the HLDA is dropped by the processor at the trailing edge
of the next clock.
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53. Minimum Mode 8086 System (cont..)
Clk
HOLD
HLDA
Bus Request and Bus Grant Timings in Minimum Mode System
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54. Maximum Mode 8086 System
• In the maximum mode, the 8086 is operated by strapping
the MN/MX pin to ground.
• In this mode, the processor derives the status signal S2, S1,
S0. Another chip called bus controller derives the control
signal using this status information .
• In the maximum mode, there may be more than one
microprocessor in the system configuration.
• The components in the system are same as in the minimum
mode system.
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55. Maximum Mode 8086 System (cont..)
• The basic function of the bus controller chip IC8288, is to
derive control signals like RD and WR ( for memory and
I/O devices), DEN, DT/R, ALE etc. using the information
by the processor on the status lines.
• The bus controller chip has input lines S2, S1, S0 and CLK.
These inputs to 8288 are driven by CPU.
• It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,
AMWC, IORC, IOWC and AIOWC. The AEN, IOB and
CEN pins are specially useful for multiprocessor systems.
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56. Maximum Mode 8086 System ( cont..)
• AEN and IOB are generally grounded. CEN pin is usually
tied to +5V. The significance of the MCE/PDEN output
depends upon the status of the IOB pin.
• If IOB is grounded, it acts as master cascade enable to
control cascade 8259A, else it acts as peripheral data
enable used in the multiple bus configurations.
• INTA pin used to issue two interrupt acknowledge pulses
to the interrupt controller or to an interrupting device.
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57. Maximum Mode 8086 System ( cont..)
• IORC, IOWC are I/O read command and I/O write
command signals respectively . These signals enable an IO
interface to read or write the data from or to the address
port.
• The MRDC, MWTC are memory read command and
memory write command signals respectively and may be
used as memory read or write signals.
• All these command signals instructs the memory to accept
or send data from or to the bus.
• For both of these write command signals, the advanced
signals namely AIOWC and AMWTC are available.
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58. Maximum Mode 8086 System ( cont..)
• They also serve the same purpose, but are activated one
clock cycle earlier than the IOWC and MWTC signals
respectively.
• The maximum mode system timing diagrams are divided
in two portions as read (input) and write (output) timing
diagrams.
• The address/data and address/status timings are similar to
the minimum mode.
• ALE is asserted in T1, just like minimum mode. The only
difference lies in the status signal used and the available
control and advanced command signals.
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59. Maximum Mode 8086 System ( cont..)
Clk
S0
Reset
Clk
Generator
RDY 8284
DEN
DT/ R
S1
IORC
8288
IOWTC
S2
MWTC
AEN
IOB
CEN ALE MRDC
S0
S1
S2
Reset
Clk
Ready
+ 5V
8086
AD6-AD15
A16-A19
CLK
A/D
Latches
Address bus
G
DIR
Data
buffer
BHE A0
Add bus
DT/R
DEN
Control bus
CS0H CS0L RD
WR
Memory
CS WR RD
Peripherals
Data bus
Maximum Mode 8086 System.
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60. Maximum Mode 8086 System ( cont..)
• Here the only difference between in timing diagram
between minimum mode and maximum mode is the status
signals used and the available control and advanced
command signals.
• R0, S1, S2 are set at the beginning of bus cycle.8288 bus
controller will output a pulse as on the ALE and apply a
required signal to its DT / R pin during T1.
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61. Maximum Mode 8086 System ( cont..)
• In T2, 8288 will set DEN=1 thus enabling transceivers, and
for an input it will activate MRDC or IORC. These signals
are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is
activated from T3 to T4.
• The status bit S0 to S2 remains active until T3 and become
passive during T3 and T4.
• If reader input is not activated before T3, wait state will be
inserted between T3 and T4.
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62. Maximum Mode 8086 System ( cont..)
• Timings for RQ/ GT Signals :The request/grant response
sequence contains a series of three pulses. The
request/grant pins are checked at each rising pulse of clock
input.
• When a request is detected and if the condition for HOLD
request are satisfied, the processor issues a grant pulse over
the RQ/GT pin immediately during T4 (current) or T1
(next) state.
• When the requesting master receives this pulse, it accepts
the control of the bus, it sends a release pulse to the
processor using RQ/GT pin.
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63. Maximum Mode 8086 System ( cont..)
T1
T2
One bus cycle
T3
T4
T1
Clk
AL
E
S2 – S0
Add/Status
Add/Data
Inactive
Active
BHE, A19 – A16
Active
S7 – S3
A15 – A0
D15 – D0
MRDC
DT / R
DEN
Memory Read Timing in Maximum Mode
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64. Maximum Mode 8086 System ( cont..)
T1
T2
One bus cycle
T3
T4
T1
Clk
ALE
S2 – S0
Inactive
Active
ADD/STATUS
BHE
ADD/DATA
A15-A0
Active
S7 – S3
Data out D15 – D0
AMWC or
AIOWC
MWTC or IOWC
high
DT / R
DEN
Memory Write Timing in Maximum mode.
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65. Maximum Mode 8086 System ( cont..)
Clk
RQ / GT
Another master
request bus access
CPU grant bus
Master releases bus
RQ/GT Timings in Maximum Mode.
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66. Internal Registers of 8086 (cont..)
• The 8086 has four groups of the user accessible internal
registers. They are the instruction pointer, four data
registers, four pointer and index register, four segment
registers.
• The 8086 has a total of fourteen 16-bit registers including a
16 bit register called the status register, with 9 of bits
implemented for status and control flags.
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67. Internal Registers of 8086 (cont..)
• Most of the registers contain data/instruction offsets within
64 KB memory segment. There are four different 64 KB
segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4
segments are located the processor uses four segment
registers:
• Code segment (CS) is a 16-bit register containing address
of 64 KB segment with processor instructions. The
processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register
cannot be changed directly. The CS register is
automatically updated during far jump, far call and far
return instructions.
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68. Internal Registers of 8086 (cont..)
• Stack segment (SS) is a 16-bit register containing address
of 64KB segment with program stack. By default, the
processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in
the stack segment. SS register can be changed directly
using POP instruction.
• Data segment (DS) is a 16-bit register containing address
of 64KB segment with program data. By default, the
processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment. DS register can be changed
directly using POP and LDS instructions.
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69. Internal Registers of 8086 (cont..)
• Extra segment (ES) is a 16-bit register containing address
of 64KB segment, usually with program data. By default,
the processor assumes that the DI register references the
ES segment in string manipulation instructions. ES register
can be changed directly using POP and LES instructions.
• It is possible to change default segments used by general
and index registers by prefixing instructions with a CS, SS,
DS or ES prefix.
• All general registers of the 8086 microprocessor can be
used for arithmetic and logic operations. The general
registers are:
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70. Internal Registers of 8086 (cont..)
• Accumulator register consists of two 8-bit registers AL
and AH, which can be combined together and used as a 16bit register AX. AL in this case contains the low-order byte
of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations and string
manipulation.
• Base register consists of two 8-bit registers BL and BH,
which can be combined together and used as a 16-bit
register BX. BL in this case contains the low-order byte of
the word, and BH contains the high-order byte. BX register
usually contains a data pointer used for based, based
indexed or register indirect addressing.
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71. Internal Registers of 8086 (cont..)
• Count register consists of two 8-bit registers CL and CH,
which can be combined together and used as a 16-bit
register CX. When combined, CL register contains the
low-order byte of the word, and CH contains the highorder byte. Count register can be used in Loop, shift/rotate
instructions and as a counter in string manipulation,.
• Data register consists of two 8-bit registers DL and DH,
which can be combined together and used as a 16-bit
register DX. When combined, DL register contains the
low-order byte of the word, and DH contains the highorder byte. Data register can be used as a port number in
I/O operations. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the
initial or resulting number.
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72. Internal Registers of 8086 (cont..)
• The following registers are both general and index
registers:
• Stack Pointer (SP) is a 16-bit register pointing to program
stack.
• Base Pointer (BP) is a 16-bit register pointing to data in
stack segment. BP register is usually used for based, based
indexed or register indirect addressing.
• Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect addressing, as
well as a source data address in string manipulation
instructions.
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73. Internal Registers of 8086 (cont..)
• Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing, as
well as a destination data address in string manipulation
instructions.
Other registers:
• Instruction Pointer (IP) is a 16-bit register.
• Flags is a 16-bit register containing 9 one bit flags.
• Overflow Flag (OF) - set if the result is too large positive
number, or is too small negative number to fit into
destination operand.
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74. Internal Registers of 8086 (cont..)
• Direction Flag (DF) - if set then string manipulation
instructions will auto-decrement index registers. If cleared
then the index registers will be auto-incremented.
• Interrupt-enable Flag (IF) - setting this bit enables
maskable interrupts.
• Single-step Flag (TF) - if set then single-step interrupt will
occur after the next instruction.
• Sign Flag (SF) - set if the most significant bit of the result
is set.
• Zero Flag (ZF) - set if the result is zero.
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75. Internal Registers of 8086
• Auxiliary carry Flag (AF) - set if there was a carry from
or borrow to bits 0-3 in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits) in
the low-order byte of the result is even.
• Carry Flag (CF) - set if there was a carry from or borrow
to the most significant bit during last result calculation.
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76. Addressing Modes (cont..)
• Implied - the data value/data address is implicitly
associated with the instruction.
• Register - references the data in a register or in a register
pair.
• Immediate - the data is provided in the instruction.
• Direct - the instruction operand specifies the memory
address where data is located.
• Register indirect - instruction specifies a register
containing an address, where data is located. This
addressing mode works with SI, DI, BX and BP registers.
• Based :- 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP), the resulting value
is a pointer to location where data resides.
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77. Addressing Modes
• Indexed :- 8-bit or 16-bit instruction operand is added to
the contents of an index register (SI or DI), the resulting
value is a pointer to location where data resides.
• Based Indexed :- the contents of a base register (BX or
BP) is added to the contents of an index register (SI or DI),
the resulting value is a pointer to location where data
resides.
• Based Indexed with displacement :- 8-bit or 16-bit
instruction operand is added to the contents of a base
register (BX or BP) and index register (SI or DI), the
resulting value is a pointer to location where data resides.
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78. Memory (cont..)
• Program, data and stack memories occupy the same
memory space. As the most of the processor instructions
use 16-bit pointers the processor can effectively address
only 64 KB of memory.
• To access memory outside of 64 KB the CPU uses special
segment registers to specify where the code, stack and data
64 KB segments are positioned within 1 MB of memory
(see the "Registers" section below).
• 16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
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79. Memory (cont..)
• 32-bit addresses are stored in "segment: offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
• Physical memory address pointed by segment: offset pair
is calculated as:
• address = (<segment> * 16) + <offset>
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80. Memory (cont..)
• Program memory - program can be located anywhere in
memory. Jump and call instructions can be used for short
jumps within currently selected 64 KB code segment, as
well as for far jumps anywhere within 1 MB of memory.
• All conditional jump instructions can be used to jump
within approximately +127 to -127 bytes from current
instruction.
• Data memory - the processor can access data in any one
out of 4 available segments, which limits the size of
accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
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81. Memory (cont..)
• Accessing data from the Data, Code, Stack or Extra
segments can be usually done by prefixing instructions
with the DS:, CS:, SS: or ES: (some registers and
instructions by default may use the ES or SS segments
instead of DS segment).
• Word data can be located at odd or even byte boundaries.
The processor uses two memory accesses to read 16-bit
word located at odd byte boundaries. Reading word data
from even byte boundaries requires only one memory
access.
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82. Memory
• Stack memory can be placed anywhere in memory. The
stack can be located at odd memory addresses, but it is not
recommended for performance reasons (see "Data
Memory" above).
Reserved locations:
• 0000h - 03FFh are reserved for interrupt vectors. Each
interrupt vector is a 32-bit pointer in format segment:
offset.
• FFFF0h - FFFFFh - after RESET the processor always
starts program execution at the FFFF0h address.
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83. Interrupts (cont..)
The processor has the following interrupts:
• INTR is a maskable hardware interrupt. The interrupt can
be enabled/disabled using STI/CLI instructions or using
more complicated method of updating the FLAGS register
with the help of the POPF instruction.
• When an interrupt occurs, the processor stores FLAGS
register into stack, disables further interrupts, fetches from
the bus one byte representing interrupt type, and jumps to
interrupt processing routine address of which is stored in
location 4 * <interrupt type>. Interrupt processing routine
should return with the IRET instruction.
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84. Interrupts (cont..)
• NMI is a non-maskable interrupt. Interrupt is processed in
the same way as the INTR interrupt. Interrupt type of the
NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority
then the maskable interrupt.
• Software interrupts can be caused by:
• INT instruction - breakpoint interrupt. This is a type 3
interrupt.
• INT <interrupt number> instruction - any one interrupt
from available 256 interrupts.
• INTO instruction - interrupt on overflow
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85. Interrupts
• Single-step interrupt - generated if the TF flag is set. This
is a type 1 interrupt. When the CPU processes this
interrupt it clears TF flag before calling the interrupt
processing routine.
• Processor exceptions: Divide Error (Type 0), Unused
Opcode (type 6) and Escape opcode (type 7).
• Software interrupt processing is the same as for the
hardware interrupts.
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