This document provides a summary of an individual's qualifications and experience in digital and analog VLSI design. It includes their educational background with an M.Tech from IIT Roorkee and B.Tech from Jaipur Engineering College. Research publications and projects are listed, including developing a Verilog-A compact model for vertical silicon nanowire device simulation and standard cell library development for a 15nm technology node. Relevant skills include HSPICE, Verilog-A, Verilog, C programming, and digital and analog VLSI courses.